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114 lines
3.6 KiB
114 lines
3.6 KiB
/*
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* Defines for ADM5120 built in ethernet switch driver
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*
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* Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
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*
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* Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
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* Copyright ADMtek Inc.
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*/
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#ifndef _INCLUDE_ADM5120SW_H_
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#define _INCLUDE_ADM5120SW_H_
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#define SW_BASE KSEG1ADDR(0x12000000)
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#define SW_DEVS 6
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#define ETH_TX_TIMEOUT HZ*400
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#define ETH_FCS 4;
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#define ADM5120_CODE 0x00 /* CPU description */
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#define ADM5120_CODE_PQFP 0x20000000 /* package type */
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#define ADM5120_SW_CONF 0x20 /* Switch configuration register */
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#define ADM5120_SW_CONF_BPM 0x00300000 /* Mask for backpressure mode */
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#define ADM5120_CPUP_CONF 0x24 /* CPU port config */
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#define ADM5120_DISCCPUPORT 0x00000001 /* disable cpu port */
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#define ADM5120_CRC_PADDING 0x00000002 /* software crc */
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#define ADM5120_BTM 0x00000004 /* bridge test mode */
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#define ADM5120_DISUNSHIFT 9
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#define ADM5120_DISUNALL 0x00007e00 /* disable unknown from all */
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#define ADM5120_DISMCSHIFT 16
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#define ADM5120_DISMCALL 0x003f0000 /* disable multicast from all */
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#define ADM5120_PORT_CONF0 0x28
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#define ADM5120_ENMC 0x00003f00 /* Enable MC routing (ex cpu) */
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#define ADM5120_ENBP 0x003f0000 /* Enable Back Pressure */
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#define ADM5120_PORTDISALL 0x0000003F
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#define ADM5120_VLAN_GI 0x40 /* VLAN settings */
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#define ADM5120_VLAN_GII 0x44
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#define ADM5120_SEND_TRIG 0x48
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#define ADM5120_SEND_TRIG_L 0x00000001
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#define ADM5120_SEND_TRIG_H 0x00000002
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#define ADM5120_MAC_WT0 0x58
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#define ADM5120_MAC_WRITE 0x00000001
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#define ADM5120_MAC_WRITE_DONE 0x00000002
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#define ADM5120_VLAN_EN 0x00000040
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#define ADM5120_MAC_WT1 0x5c
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#define ADM5120_BW_CTL0 0x60 /* Bandwidth control 0 */
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#define ADM5120_BW_CTL1 0x64 /* Bandwidth control 1 */
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#define ADM5120_PHY_CNTL2 0x7c
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#define ADM5120_AUTONEG 0x0000001f /* Auto negotiate */
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#define ADM5120_NORMAL 0x01f00000 /* PHY normal mode */
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#define ADM5120_AUTOMDIX 0x3e000000 /* Auto MDIX */
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#define ADM5120_PHY_CNTL3 0x80
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#define ADM5120_PHY_NTH 0x00000400
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#define ADM5120_PRI_CNTL 0x84
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#define ADM5120_INT_ST 0xb0
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#define ADM5120_INT_RXH 0x0000004
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#define ADM5120_INT_RXL 0x0000008
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#define ADM5120_INT_HFULL 0x0000010
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#define ADM5120_INT_LFULL 0x0000020
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#define ADM5120_INT_TXH 0x0000001
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#define ADM5120_INT_TXL 0x0000002
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#define ADM5120_INT_MASK 0xb4
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#define ADM5120_INTMASKALL 0x1FDEFFF /* All interrupts */
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#define ADM5120_INTHANDLE (ADM5120_INT_RXH | ADM5120_INT_RXL | \
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ADM5120_INT_HFULL | ADM5120_INT_LFULL | \
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ADM5120_INT_TXH | ADM5120_INT_TXL)
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#define ADM5120_SEND_HBADDR 0xd0
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#define ADM5120_SEND_LBADDR 0xd4
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#define ADM5120_RECEIVE_HBADDR 0xd8
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#define ADM5120_RECEIVE_LBADDR 0xdc
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struct adm5120_dma {
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u32 data;
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u32 cntl;
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u32 len;
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u32 status;
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} __attribute__ ((packed));
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#define ADM5120_DMA_MASK 0x01ffffff
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#define ADM5120_DMA_OWN 0x80000000 /* buffer owner */
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#define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */
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#define ADM5120_DMA_ADDR(ptr) ((u32)(ptr) & ADM5120_DMA_MASK)
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#define ADM5120_DMA_PORTID 0x00007000
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#define ADM5120_DMA_PORTSHIFT 12
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#define ADM5120_DMA_LEN 0x07ff0000
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#define ADM5120_DMA_LENSHIFT 16
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#define ADM5120_DMA_FCSERR 0x00000008
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#define ADM5120_DMA_TXH 2
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#define ADM5120_DMA_TXL 64
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#define ADM5120_DMA_RXH 2
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#define ADM5120_DMA_RXL 64
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#define ADM5120_DMA_RXSIZE 1550
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#define ADM5120_DMA_EXTRA 20
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struct adm5120_sw {
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int port;
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struct net_device_stats stats;
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};
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#define SIOCSMATRIX SIOCDEVPRIVATE
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#define SIOCGMATRIX SIOCDEVPRIVATE+1
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#define SIOCGADMINFO SIOCDEVPRIVATE+2
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#define SIOCGETBW SIOCDEVPRIVATE+3
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#define SIOCSETBW SIOCDEVPRIVATE+4
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struct adm5120_sw_info {
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u16 magic;
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u16 ports;
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u16 vlan;
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};
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#endif /* _INCLUDE_ADM5120SW_H_ */
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