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143 lines
3.3 KiB
143 lines
3.3 KiB
/*
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* $Id$
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*
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* ADM5120 specific PCI operations
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*
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#define DEBUG 0
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#if DEBUG
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#define DBG(f, ...) printk(f, ## __VA_ARGS__ )
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#else
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#define DBG(f, ...)
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#endif
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#define PCI_ENABLE 0x80000000
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static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
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static inline void write_cfgaddr(u32 addr)
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{
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*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR) = (addr | PCI_ENABLE);
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}
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static inline void write_cfgdata(u32 data)
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{
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*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA) = data;
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}
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static inline u32 read_cfgdata(void)
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{
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return (*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
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{
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return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
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(where & 0xFC));
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*val = data;
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DBG(", 0x%08X returned\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((val & 0xFF) << s);
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break;
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case 2:
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s = ((where & 2) << 4);
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data &= ~(0xFFFF << s);
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data |= ((val & 0xFFFF) << s);
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break;
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case 4:
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data = val;
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break;
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}
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write_cfgdata(data);
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DBG(", 0x%08X written\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops adm5120_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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