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372 lines
11 KiB
372 lines
11 KiB
--- a/drivers/ssb/Kconfig
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+++ b/drivers/ssb/Kconfig
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@@ -139,7 +139,7 @@ config SSB_DRIVER_MIPS
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config SSB_SFLASH
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bool "SSB serial flash support"
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- depends on SSB_DRIVER_MIPS && BROKEN
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+ depends on SSB_DRIVER_MIPS
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default y
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# Assumption: We are on embedded, if we compile the MIPS core.
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--- a/drivers/ssb/driver_chipcommon_sflash.c
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+++ b/drivers/ssb/driver_chipcommon_sflash.c
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@@ -1,14 +1,35 @@
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/*
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* Sonics Silicon Backplane
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* ChipCommon serial flash interface
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+ * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
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+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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+ * Copyright 2010, Broadcom Corporation
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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#include <linux/ssb/ssb.h>
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+#include <linux/ssb/ssb_driver_chipcommon.h>
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#include "ssb_private.h"
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+#define NUM_RETRIES 3
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+
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+static struct resource ssb_sflash_resource = {
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+ .name = "ssb_sflash",
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+ .start = SSB_FLASH2,
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+ .end = 0,
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+ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
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+};
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+
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+struct platform_device ssb_sflash_dev = {
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+ .name = "bcm47xx-sflash",
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+ .resource = &ssb_sflash_resource,
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+ .num_resources = 1,
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+};
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+
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struct ssb_sflash_tbl_e {
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char *name;
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u32 id;
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@@ -16,7 +37,7 @@ struct ssb_sflash_tbl_e {
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u16 numblocks;
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};
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-static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
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+static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
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{ "M25P20", 0x11, 0x10000, 4, },
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{ "M25P40", 0x12, 0x10000, 8, },
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@@ -27,7 +48,7 @@ static struct ssb_sflash_tbl_e ssb_sflas
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{ 0 },
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};
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-static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
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+static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
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{ "SST25WF512", 1, 0x1000, 16, },
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{ "SST25VF512", 0x48, 0x1000, 16, },
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{ "SST25WF010", 2, 0x1000, 32, },
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@@ -45,7 +66,7 @@ static struct ssb_sflash_tbl_e ssb_sflas
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{ 0 },
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};
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-static struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
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+static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
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{ "AT45DB011", 0xc, 256, 512, },
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{ "AT45DB021", 0x14, 256, 1024, },
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{ "AT45DB041", 0x1c, 256, 2048, },
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@@ -70,10 +91,186 @@ static void ssb_sflash_cmd(struct ssb_ch
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pr_err("SFLASH control command failed (timeout)!\n");
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}
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+static void ssb_sflash_write_u8(struct ssb_chipcommon *chipco, u32 offset, u8 byte)
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+{
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset);
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHDATA, byte);
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+}
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+
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+/* Poll for command completion. Returns zero when complete. */
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+static int ssb_sflash_poll(struct bcm47xxsflash *dev, u32 offset)
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+{
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+ struct ssb_chipcommon *chipco = dev->scc;
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+
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+ if (offset >= chipco->sflash.size)
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+ return -22;
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+
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+ switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ /* Check for ST Write In Progress bit */
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_RDSR);
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+ return chipco_read32(chipco, SSB_CHIPCO_FLASHDATA)
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+ & SSB_CHIPCO_FLASHDATA_ST_WIP;
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ /* Check for Atmel Ready bit */
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_STATUS);
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+ return !(chipco_read32(chipco, SSB_CHIPCO_FLASHDATA)
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+ & SSB_CHIPCO_FLASHDATA_AT_READY);
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+ }
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+
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+ return 0;
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+}
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+
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+
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+static int sflash_st_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ int written = 1;
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+ struct ssb_chipcommon *chipco = dev->scc;
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+
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+ /* Enable writes */
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_WREN);
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+ ssb_sflash_write_u8(chipco, offset, *buf++);
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+ /* Issue a page program with CSA bit set */
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_CSA | SSB_CHIPCO_FLASHCTL_ST_PP);
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+ offset++;
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+ len--;
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+ while (len > 0) {
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+ if ((offset & 255) == 0) {
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+ /* Page boundary, poll droping cs and return */
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHCTL, 0);
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+ udelay(1);
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+ if (!ssb_sflash_poll(dev, offset)) {
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+ /* Flash rejected command */
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+ return -EAGAIN;
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+ }
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+ return written;
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+ } else {
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+ /* Write single byte */
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+ ssb_sflash_cmd(chipco,
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+ SSB_CHIPCO_FLASHCTL_ST_CSA |
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+ *buf++);
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+ }
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+ written++;
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+ offset++;
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+ len--;
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+ }
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+ /* All done, drop cs & poll */
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHCTL, 0);
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+ udelay(1);
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+ if (!ssb_sflash_poll(dev, offset)) {
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+ /* Flash rejected command */
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+ return -EAGAIN;
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+ }
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+ return written;
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+}
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+
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+static int sflash_at_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ struct ssb_chipcommon *chipco = dev->scc;
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+ u32 page, byte, mask;
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+ int ret = 0;
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+
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+ mask = dev->blocksize - 1;
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+ page = (offset & ~mask) << 1;
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+ byte = offset & mask;
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+ /* Read main memory page into buffer 1 */
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+ if (byte || (len < dev->blocksize)) {
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+ int i = 100;
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, page);
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD);
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+ /* 250 us for AT45DB321B */
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+ while (i > 0 && ssb_sflash_poll(dev, offset)) {
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+ udelay(10);
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+ i--;
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+ }
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+ BUG_ON(!ssb_sflash_poll(dev, offset));
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+ }
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+ /* Write into buffer 1 */
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+ for (ret = 0; (ret < (int)len) && (byte < dev->blocksize); ret++) {
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+ ssb_sflash_write_u8(chipco, byte++, *buf++);
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE);
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+ }
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+ /* Write buffer 1 into main memory page */
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, page);
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM);
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+
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+ return ret;
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+}
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+
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+/* Write len bytes starting at offset into buf. Returns number of bytes
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+ * written. Caller should poll for completion.
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+ */
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+static int ssb_sflash_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ int ret = 0, tries = NUM_RETRIES;
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+ struct ssb_chipcommon *chipco = dev->scc;
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+
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+ if (!len)
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+ return 0;
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+
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+ if ((offset + len) > chipco->sflash.size)
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+ return -EINVAL;
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+
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+ switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ do {
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+ ret = sflash_st_write(dev, offset, len, buf);
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+ tries--;
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+ } while (ret == -EAGAIN && tries > 0);
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+
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+ if (ret == -EAGAIN && tries == 0) {
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+ pr_info("ST Flash rejected write\n");
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+ ret = -EIO;
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+ }
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+ break;
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ ret = sflash_at_write(dev, offset, len, buf);
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+/* Erase a region. Returns number of bytes scheduled for erasure.
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+ * Caller should poll for completion.
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+ */
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+static int ssb_sflash_erase(struct bcm47xxsflash *dev, u32 offset)
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+{
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+ struct ssb_chipcommon *chipco = dev->scc;
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+
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+ if (offset >= chipco->sflash.size)
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+ return -EINVAL;
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+
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+ switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_WREN);
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset);
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+ /* Newer flashes have "sub-sectors" which can be erased independently
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+ * with a new command: ST_SSE. The ST_SE command erases 64KB just as
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+ * before.
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+ */
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+ if (dev->blocksize < (64 * 1024))
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_SSE);
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+ else
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_SE);
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+ return dev->blocksize;
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset << 1);
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+ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE);
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+ return dev->blocksize;
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+ }
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+
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+ return 0;
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+}
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+
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/* Initialize serial flash access */
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int ssb_sflash_init(struct ssb_chipcommon *cc)
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{
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- struct ssb_sflash_tbl_e *e;
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+ struct bcm47xxsflash *sflash = &cc->sflash;
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+ const struct ssb_sflash_tbl_e *e;
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u32 id, id2;
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switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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@@ -131,10 +328,26 @@ int ssb_sflash_init(struct ssb_chipcommo
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return -ENOTSUPP;
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}
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- pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
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- e->name, e->blocksize, e->numblocks);
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-
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- pr_err("Serial flash support is not implemented yet!\n");
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+ sflash->window = SSB_FLASH2;
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+ sflash->blocksize = e->blocksize;
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+ sflash->numblocks = e->numblocks;
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+ sflash->size = sflash->blocksize * sflash->numblocks;
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+ sflash->present = true;
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+ sflash->poll = ssb_sflash_poll;
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+ sflash->write = ssb_sflash_write;
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+ sflash->erase = ssb_sflash_erase;
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+ sflash->type = BCM47XX_SFLASH_SSB;
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+ sflash->scc = cc;
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+
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+ pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
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+ e->name, sflash->size / 1024, sflash->blocksize,
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+ sflash->numblocks);
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+
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+ /* Prepare platform device, but don't register it yet. It's too early,
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+ * malloc (required by device_private_init) is not available yet. */
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+ ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
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+ sflash->size;
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+ ssb_sflash_dev.dev.platform_data = sflash;
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- return -ENOTSUPP;
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+ return 0;
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}
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -545,6 +545,15 @@ static int ssb_devices_register(struct s
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dev_idx++;
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}
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+#ifdef CONFIG_SSB_SFLASH
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+ if (bus->chipco.sflash.present) {
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+ err = platform_device_register(&ssb_sflash_dev);
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+ if (err)
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+ ssb_printk(KERN_ERR PFX
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+ "Error registering serial flash\n");
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+ }
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+#endif
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+
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#ifdef CONFIG_SSB_DRIVER_MIPS
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if (bus->mipscore.pflash.present) {
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err = platform_device_register(&ssb_pflash_dev);
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--- a/drivers/ssb/ssb_private.h
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+++ b/drivers/ssb/ssb_private.h
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@@ -231,6 +231,7 @@ extern u32 ssb_chipco_watchdog_timer_set
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/* driver_chipcommon_sflash.c */
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#ifdef CONFIG_SSB_SFLASH
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int ssb_sflash_init(struct ssb_chipcommon *cc);
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+extern struct platform_device ssb_sflash_dev;
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#else
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static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
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{
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -13,6 +13,8 @@
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* Licensed under the GPL version 2. See COPYING for details.
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*/
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+#include <linux/mtd/bcm47xxsflash.h>
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+
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/** ChipCommon core registers. **/
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#define SSB_CHIPCO_CHIPID 0x0000
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@@ -121,6 +123,17 @@
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#define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START
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#define SSB_CHIPCO_FLASHADDR 0x0044
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#define SSB_CHIPCO_FLASHDATA 0x0048
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+/* Status register bits for ST flashes */
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+#define SSB_CHIPCO_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
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+#define SSB_CHIPCO_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
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+#define SSB_CHIPCO_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
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+#define SSB_CHIPCO_FLASHDATA_ST_BP_SHIFT 2
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+#define SSB_CHIPCO_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
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+/* Status register bits for Atmel flashes */
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+#define SSB_CHIPCO_FLASHDATA_AT_READY 0x80
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+#define SSB_CHIPCO_FLASHDATA_AT_MISMATCH 0x40
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+#define SSB_CHIPCO_FLASHDATA_AT_ID_MASK 0x38
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+#define SSB_CHIPCO_FLASHDATA_AT_ID_SHIFT 3
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#define SSB_CHIPCO_BCAST_ADDR 0x0050
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#define SSB_CHIPCO_BCAST_DATA 0x0054
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#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
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@@ -504,7 +517,7 @@
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#define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
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#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
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#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
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-#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
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+#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00D9 /* Deep Power-down */
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#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
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#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
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#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
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@@ -595,6 +608,9 @@ struct ssb_chipcommon {
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struct ssb_chipcommon_pmu pmu;
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u32 ticks_per_ms;
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u32 max_timer_ms;
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+#ifdef CONFIG_SSB_SFLASH
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+ struct bcm47xxsflash sflash;
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+#endif
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};
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static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
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