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176 lines
6.8 KiB
176 lines
6.8 KiB
From 9a16718a325c1969422eb9d9b644eb89ce06692c Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 3 Jul 2011 03:41:02 +0200
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Subject: [PATCH 46/79] MIPS: BCM63XX: Add PCIe register set definitions
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 ++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 +++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 +++++++++++++++++++++
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3 files changed, 69 insertions(+)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
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RSET_USBH_PRIV,
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RSET_MPI,
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RSET_PCMCIA,
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+ RSET_PCIE,
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RSET_DSL,
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RSET_ENET0,
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RSET_ENET1,
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@@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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+#define BCM_6328_PCIE_BASE (0xb0e40000)
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#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6328_DSL_BASE (0xb0001900)
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#define BCM_6328_UBUS_BASE (0xdeadbeef)
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@@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xfffe3160)
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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+#define BCM_6338_PCIE_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_UBUS_BASE (0xdeadbeef)
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@@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_ENETSW_BASE (0xdeadbeef)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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#define BCM_6345_MPI_BASE (0xfffe2000)
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+#define BCM_6345_PCIE_BASE (0xdeadbeef)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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@@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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+#define BCM_6348_PCIE_BASE (0xdeadbeef)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_M2M_BASE (0xfffe2800)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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@@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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+#define BCM_6358_PCIE_BASE (0xdeadbeef)
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6358_M2M_BASE (0xdeadbeef)
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#define BCM_6358_DSL_BASE (0xfffe3000)
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@@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
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#define BCM_6368_MPI_BASE (0xb0001000)
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#define BCM_6368_PCMCIA_BASE (0xb0001054)
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+#define BCM_6368_PCIE_BASE (0xdeadbeef)
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#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6368_M2M_BASE (0xdeadbeef)
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#define BCM_6368_DSL_BASE (0xdeadbeef)
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@@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
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__GEN_RSET_BASE(__cpu, USBH_PRIV) \
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__GEN_RSET_BASE(__cpu, MPI) \
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__GEN_RSET_BASE(__cpu, PCMCIA) \
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+ __GEN_RSET_BASE(__cpu, PCIE) \
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__GEN_RSET_BASE(__cpu, DSL) \
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__GEN_RSET_BASE(__cpu, ENET0) \
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__GEN_RSET_BASE(__cpu, ENET1) \
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@@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
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[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
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[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
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+ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
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[RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
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[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
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[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -40,6 +40,10 @@
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#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
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BCM_CB_MEM_SIZE - 1)
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+#define BCM_PCIE_MEM_BASE_PA 0x10f00000
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+#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
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+#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
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+ BCM_PCIE_MEM_SIZE - 1)
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/*
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* Internal registers are accessed through KSEG3
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@@ -85,6 +89,8 @@
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#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
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#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
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#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
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+#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
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+#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
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#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
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#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
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#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1163,6 +1163,9 @@
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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+#define MISC_SERDES_CTRL_REG 0x0
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+#define SERDES_PCIE_EN (1 << 0)
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+#define SERDES_PCIE_EXD_EN (1 << 15)
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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@@ -1170,4 +1173,55 @@
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#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
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+/*************************************************************************
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+ * _REG relative to RSET_PCIE
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+ *************************************************************************/
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+
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+#define PCIE_CONFIG2_REG 0x408
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+#define CONFIG2_BAR1_SIZE_EN 1
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+#define CONFIG2_BAR1_SIZE_MASK 0xf
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+
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+#define PCIE_IDVAL3_REG 0x43c
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+#define IDVAL3_CLASS_CODE_MASK 0xffffff
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+#define IDVAL3_SUBCLASS_SHIFT 8
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+#define IDVAL3_CLASS_SHIFT 16
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+
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+#define PCIE_DLSTATUS_REG 0x1048
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+#define DLSTATUS_PHYLINKUP (1 << 13)
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+
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+#define PCIE_BRIDGE_OPT1_REG 0x2820
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+#define OPT1_RD_BE_OPT_EN (1 << 7)
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+#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
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+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
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+#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
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+
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+#define PCIE_BRIDGE_OPT2_REG 0x2824
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+#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
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+#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
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+#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
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+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
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+#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
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+
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+#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
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+#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
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+#define BASEMASK_REMAP_EN (1 << 0)
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+#define BASEMASK_SWAP_EN (1 << 1)
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+#define BASEMASK_MASK_SHIFT 4
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+#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
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+#define BASEMASK_BASE_SHIFT 20
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+#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
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+
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+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
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+#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
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+#define REBASE_ADDR_BASE_SHIFT 20
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+#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
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+
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+#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
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+#define PCIE_RC_INT_A (1 << 0)
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+#define PCIE_RC_INT_B (1 << 1)
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+#define PCIE_RC_INT_C (1 << 2)
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+#define PCIE_RC_INT_D (1 << 3)
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+
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+#define PCIE_DEVICE_OFFSET 0x8000
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+
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#endif /* BCM63XX_REGS_H_ */
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