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250 lines
5.2 KiB
250 lines
5.2 KiB
/******************************************************************************
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**
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** FILE NAME : ifxmips_deu_danube.h
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** PROJECT : IFX UEIP
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** MODULES : DEU Module for Danube
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**
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** DATE : September 8, 2009
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** AUTHOR : Mohammad Firdaus
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** DESCRIPTION : Data Encryption Unit Driver
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** COPYRIGHT : Copyright (c) 2009
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 08,Sept 2009 Mohammad Firdaus Initial UEIP release
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*******************************************************************************/
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/*!
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\defgroup IFX_DEU IFX_DEU_DRIVERS
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\ingroup API
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\brief deu driver module
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*/
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/*!
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\file ifxmips_deu_danube.h
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\brief board specific driver header file for danube
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*/
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/*!
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\defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS
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\ingroup IFX_DEU
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\brief board specific deu header files
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*/
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#ifndef IFXMIPS_DEU_DANUBE_H
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#define IFXMIPS_DEU_DANUBE_H
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/* Project Header Files */
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <asm/byteorder.h>
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#include <crypto/algapi.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/scatterlist.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include "ifxmips_deu.h"
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#define INPUT_ENDIAN_SWAP(input) input_swap(input)
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#define DEU_ENDIAN_SWAP(input) endian_swap(input)
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#define FIND_DEU_CHIP_VERSION chip_version()
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#define AES_DMA_MISC_CONFIG()
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#define CLC_START IFX_DEU_CLK
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#define AES_START IFX_AES_CON
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#define DES_3DES_START IFX_DES_CON
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#define AES_INIT 0
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#define DES_INIT 1
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#define SHA1_INIT 2
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#define MD5_INIT 3
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#define WAIT_AES_DMA_READY() \
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do { \
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int i; \
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volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
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volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
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for (i = 0; i < 10; i++) \
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udelay(DELAY_PERIOD); \
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while (dma->controlr.BSY) {}; \
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while (aes->controlr.BUS) {}; \
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} while (0)
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#define WAIT_DES_DMA_READY() \
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do { \
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int i; \
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volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
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volatile struct des_t *des = (struct des_t *) DES_3DES_START; \
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for (i = 0; i < 10; i++) \
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udelay(DELAY_PERIOD); \
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while (dma->controlr.BSY) {}; \
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while (des->controlr.BUS) {}; \
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} while (0)
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#define SHA_HASH_INIT \
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do { \
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volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
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hash->controlr.SM = 1; \
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hash->controlr.ALGO = 0; \
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hash->controlr.INIT = 1; \
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} while(0)
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/* DEU STRUCTURES */
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struct clc_controlr_t {
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u32 Res:26;
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u32 FSOE:1;
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u32 SBWE:1;
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u32 EDIS:1;
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u32 SPEN:1;
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u32 DISS:1;
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u32 DISR:1;
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};
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struct des_t {
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struct des_controlr { //10h
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u32 KRE:1;
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u32 reserved1:5;
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u32 GO:1;
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u32 STP:1;
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u32 Res2:6;
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u32 NDC:1;
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u32 ENDI:1;
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u32 Res3:2;
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u32 F:3;
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u32 O:3;
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u32 BUS:1;
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u32 DAU:1;
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u32 ARS:1;
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u32 SM:1;
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u32 E_D:1;
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u32 M:3;
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} controlr;
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u32 IHR; //14h
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u32 ILR; //18h
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u32 K1HR; //1c
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u32 K1LR; //
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u32 K2HR;
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u32 K2LR;
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u32 K3HR;
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u32 K3LR; //30h
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u32 IVHR; //34h
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u32 IVLR; //38
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u32 OHR; //3c
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u32 OLR; //40
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};
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struct aes_t {
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struct aes_controlr {
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u32 KRE:1;
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u32 reserved1:4;
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u32 PNK:1;
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u32 GO:1;
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u32 STP:1;
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u32 reserved2:6;
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u32 NDC:1;
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u32 ENDI:1;
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u32 reserved3:2;
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u32 F:3; //fbs
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u32 O:3; //om
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u32 BUS:1; //bsy
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u32 DAU:1;
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u32 ARS:1;
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u32 SM:1;
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u32 E_D:1;
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u32 KV:1;
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u32 K:2; //KL
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} controlr;
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u32 ID3R; //80h
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u32 ID2R; //84h
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u32 ID1R; //88h
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u32 ID0R; //8Ch
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u32 K7R; //90h
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u32 K6R; //94h
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u32 K5R; //98h
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u32 K4R; //9Ch
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u32 K3R; //A0h
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u32 K2R; //A4h
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u32 K1R; //A8h
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u32 K0R; //ACh
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u32 IV3R; //B0h
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u32 IV2R; //B4h
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u32 IV1R; //B8h
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u32 IV0R; //BCh
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u32 OD3R; //D4h
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u32 OD2R; //D8h
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u32 OD1R; //DCh
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u32 OD0R; //E0h
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};
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struct deu_hash_t {
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struct hash_controlr {
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u32 reserved1:5;
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u32 KHS:1;
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u32 GO:1;
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u32 INIT:1;
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u32 reserved2:6;
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u32 NDC:1;
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u32 ENDI:1;
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u32 reserved3:7;
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u32 DGRY:1;
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u32 BSY:1;
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u32 reserved4:1;
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u32 IRCL:1;
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u32 SM:1;
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u32 KYUE:1;
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u32 HMEN:1;
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u32 SSEN:1;
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u32 ALGO:1;
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} controlr;
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u32 MR; //B4h
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u32 D1R; //B8h
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u32 D2R; //BCh
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u32 D3R; //C0h
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u32 D4R; //C4h
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u32 D5R; //C8h
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u32 dummy; //CCh
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u32 KIDX; //D0h
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u32 KEY; //D4h
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u32 DBN; //D8h
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};
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struct deu_dma_t {
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struct dma_controlr {
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u32 reserved1:22;
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u32 BS:2;
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u32 BSY:1;
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u32 reserved2:1;
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u32 ALGO:2;
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u32 RXCLS:2;
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u32 reserved3:1;
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u32 EN:1;
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} controlr;
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};
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#endif /* IFXMIPS_DEU_DANUBE_H */
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