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181 lines
6.6 KiB
181 lines
6.6 KiB
From 924f021c0344554a4b61746e5c4dcfc91d618ce2 Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <yunhui.cui@nxp.com>
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Date: Thu, 18 Feb 2016 16:41:53 +0800
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Subject: [PATCH 105/113] mtd: spi-nor: add DDR quad read support
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This patch adds the DDR quad read support by the following:
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[1] add SPI_NOR_DDR_QUAD read mode.
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[2] add DDR Quad read opcodes:
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SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D
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[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
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Currently it only works for Spansion NOR.
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[4] set dummy with 6 for Spansion family
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Test this patch for Spansion s25fl128s NOR flash.
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Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 53 ++++++++++++++++++++++++++++++++++++-----
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include/linux/mtd/spi-nor.h | 8 +++++--
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2 files changed, 53 insertions(+), 8 deletions(-)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -73,7 +73,8 @@ struct flash_info {
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#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
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-#define USE_FSR 0x80 /* use flag status register */
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+#define SPI_NOR_DDR_QUAD_READ 0x80 /* Flash supports DDR Quad Read */
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+#define USE_FSR 0x100 /* use flag status register */
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#define SPI_NOR_HAS_LOCK 0x100 /* Flash supports lock/unlock via SR */
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};
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@@ -145,13 +146,17 @@ static int read_cr(struct spi_nor *nor)
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* It can be used to support more commands with
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* different dummy cycle requirements.
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*/
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-static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
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+static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor,
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+ const struct flash_info *info)
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{
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switch (nor->flash_read) {
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case SPI_NOR_FAST:
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case SPI_NOR_DUAL:
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case SPI_NOR_QUAD:
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return 8;
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+ case SPI_NOR_DDR_QUAD:
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+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION)
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+ return 6;
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case SPI_NOR_NORMAL:
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return 0;
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}
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@@ -799,7 +804,8 @@ static const struct flash_info spi_nor_i
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
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+ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ
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+ | SPI_NOR_DDR_QUAD_READ) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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@@ -1188,6 +1194,23 @@ static int spansion_quad_enable(struct s
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return 0;
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}
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+static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
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+{
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+ int status;
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+
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+ switch (JEDEC_MFR(info)) {
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+ case SNOR_MFR_SPANSION:
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+ status = spansion_quad_enable(nor);
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+ if (status) {
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+ dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
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+ return status;
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+ }
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+ return status;
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
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{
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int status;
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@@ -1378,8 +1401,15 @@ int spi_nor_scan(struct spi_nor *nor, co
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if (info->flags & SPI_NOR_NO_FR)
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nor->flash_read = SPI_NOR_NORMAL;
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- /* Quad/Dual-read mode takes precedence over fast/normal */
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- if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
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+ /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
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+ if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
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+ ret = set_ddr_quad_mode(nor, info);
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+ if (ret) {
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+ dev_err(dev, "DDR quad mode not supported\n");
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+ return ret;
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+ }
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+ nor->flash_read = SPI_NOR_DDR_QUAD;
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+ } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
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ret = set_quad_mode(nor, info);
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if (ret) {
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dev_err(dev, "quad mode not supported\n");
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@@ -1392,6 +1422,14 @@ int spi_nor_scan(struct spi_nor *nor, co
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/* Default commands */
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switch (nor->flash_read) {
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+ case SPI_NOR_DDR_QUAD:
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+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { /* Spansion */
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+ nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
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+ } else {
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+ dev_err(dev, "DDR Quad Read is not supported.\n");
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+ return -EINVAL;
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+ }
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+ break;
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case SPI_NOR_QUAD:
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nor->read_opcode = SPINOR_OP_READ_1_1_4;
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break;
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@@ -1419,6 +1457,9 @@ int spi_nor_scan(struct spi_nor *nor, co
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if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
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/* Dedicated 4-byte command set */
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switch (nor->flash_read) {
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+ case SPI_NOR_DDR_QUAD:
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+ nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
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+ break;
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case SPI_NOR_QUAD:
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nor->read_opcode = SPINOR_OP_READ4_1_1_4;
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break;
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@@ -1448,7 +1489,7 @@ int spi_nor_scan(struct spi_nor *nor, co
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return -EINVAL;
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}
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- nor->read_dummy = spi_nor_read_dummy_cycles(nor);
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+ nor->read_dummy = spi_nor_read_dummy_cycles(nor, info);
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dev_info(dev, "%s (%lld Kbytes)\n", info->name,
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(long long)mtd->size >> 10);
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -30,10 +30,11 @@
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/*
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* Note on opcode nomenclature: some opcodes have a format like
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- * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
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+ * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
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* of I/O lines used for the opcode, address, and data (respectively). The
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* FUNCTION has an optional suffix of '4', to represent an opcode which
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- * requires a 4-byte (32-bit) address.
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+ * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
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+ * DDR mode.
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*/
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/* Flash opcodes. */
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@@ -44,6 +45,7 @@
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
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+#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
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#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
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@@ -59,6 +61,7 @@
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#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
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+#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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@@ -107,6 +110,7 @@ enum read_mode {
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SPI_NOR_FAST,
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SPI_NOR_DUAL,
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SPI_NOR_QUAD,
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+ SPI_NOR_DDR_QUAD,
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};
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#define SPI_NOR_MAX_CMD_SIZE 8
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