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113 lines
3.8 KiB
113 lines
3.8 KiB
From 01ffdd37dcd3c9e526ac9135bfd289beb45f84a0 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Wed, 10 Feb 2016 16:17:29 -0800
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Subject: [PATCH] drm/vc4: Add support for feeding DSI encoders from the pixel
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valve.
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We have to set a different pixel format, which tells the hardware to
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use the pix_width field that's fed in sideband from the DSI encoder to
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divide the "pixel" clock.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 33 +++++++++++++++++++--------------
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drivers/gpu/drm/vc4/vc4_regs.h | 2 ++
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2 files changed, 21 insertions(+), 14 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -352,38 +352,40 @@ static u32 vc4_get_fifo_full_level(u32 f
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}
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/*
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- * Returns the clock select bit for the connector attached to the
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- * CRTC.
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+ * Returns the encoder attached to the CRTC.
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+ *
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+ * VC4 can only scan out to one encoder at a time, while the DRM core
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+ * allows drivers to push pixels to more than one encoder from the
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+ * same CRTC.
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*/
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-static int vc4_get_clock_select(struct drm_crtc *crtc)
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+static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
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{
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struct drm_connector *connector;
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drm_for_each_connector(connector, crtc->dev) {
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if (connector->state->crtc == crtc) {
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- struct drm_encoder *encoder = connector->encoder;
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- struct vc4_encoder *vc4_encoder =
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- to_vc4_encoder(encoder);
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-
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- return vc4_encoder->clock_select;
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+ return connector->encoder;
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}
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}
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- return -1;
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+ return NULL;
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}
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
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+ struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
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u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
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- u32 format = PV_CONTROL_FORMAT_24;
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+ bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
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+ vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
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+ u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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bool debug_dump_regs = false;
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- int clock_select = vc4_get_clock_select(crtc);
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
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@@ -439,17 +441,19 @@ static void vc4_crtc_mode_set_nofb(struc
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*/
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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+ (is_dsi ? PV_VCONTROL_DSI : 0) |
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PV_VCONTROL_INTERLACE |
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VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
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PV_VCONTROL_ODD_DELAY));
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CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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} else {
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- CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
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+ CRTC_WRITE(PV_V_CONTROL,
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+ PV_VCONTROL_CONTINUOUS |
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+ (is_dsi ? PV_VCONTROL_DSI : 0));
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}
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CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
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-
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CRTC_WRITE(PV_CONTROL,
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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VC4_SET_FIELD(vc4_get_fifo_full_level(format),
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@@ -458,7 +462,8 @@ static void vc4_crtc_mode_set_nofb(struc
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PV_CONTROL_CLR_AT_START |
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PV_CONTROL_TRIGGER_UNDERFLOW |
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PV_CONTROL_WAIT_HSTART |
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- VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
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+ VC4_SET_FIELD(vc4_encoder->clock_select,
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+ PV_CONTROL_CLK_SELECT) |
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PV_CONTROL_FIFO_CLR |
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PV_CONTROL_EN);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -190,6 +190,8 @@
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# define PV_VCONTROL_ODD_DELAY_SHIFT 6
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# define PV_VCONTROL_ODD_FIRST BIT(5)
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# define PV_VCONTROL_INTERLACE BIT(4)
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+# define PV_VCONTROL_DSI BIT(3)
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+# define PV_VCONTROL_COMMAND BIT(2)
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# define PV_VCONTROL_CONTINUOUS BIT(1)
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# define PV_VCONTROL_VIDEN BIT(0)
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