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42 lines
1.2 KiB
42 lines
1.2 KiB
--- a/arch/mips/pci/pci-mt7621.c
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+++ b/arch/mips/pci/pci-mt7621.c
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@@ -46,6 +46,7 @@
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#include <linux/version.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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+#include <asm/mips-cm.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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@@ -553,6 +554,23 @@ set_phy_for_ssc(void)
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#endif
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}
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+void setup_cm_memory_region(struct resource *mem_resource)
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+{
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+ resource_size_t mask;
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+ if (mips_cm_numiocu()) {
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+ /* FIXME: hardware doesn't accept mask values with 1s after
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+ 0s (e.g. 0xffef), so it would be great to warn if that's
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+ about to happen */
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+ mask = ~(mem_resource->end - mem_resource->start);
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+
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+ write_gcr_reg1_base(mem_resource->start);
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+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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+ printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
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+ read_gcr_reg1_base(),
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+ read_gcr_reg1_mask());
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+ }
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+}
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+
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static int mt7621_pci_probe(struct platform_device *pdev)
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{
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unsigned long val = 0;
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@@ -780,6 +798,7 @@ pcie(2/1/0) link status pcie2_num pcie1_
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}
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pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
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+ setup_cm_memory_region(mt7621_controller.mem_resource);
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register_pci_controller(&mt7621_controller);
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return 0;
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