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278 lines
8.3 KiB
278 lines
8.3 KiB
From c029c7520b110472164073f3a5b84841a2624c40 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Mon, 3 Sep 2012 01:07:40 +0200
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Subject: [PATCH 2/3] MIPS: BCM63XX: add core reset helper
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Add a reset helper for resetting the different cores.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/bcm63xx/Makefile | 6 +-
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arch/mips/bcm63xx/reset.c | 223 ++++++++++++++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 21 ++
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3 files changed, 247 insertions(+), 3 deletions(-)
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create mode 100644 arch/mips/bcm63xx/reset.c
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create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
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--- a/arch/mips/bcm63xx/Makefile
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+++ b/arch/mips/bcm63xx/Makefile
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@@ -1,6 +1,6 @@
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-obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
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- dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
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- dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
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+obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o reset.o setup.o \
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+ timer.o dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o \
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+ dev-rng.o dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += boards/
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--- /dev/null
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+++ b/arch/mips/bcm63xx/reset.c
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@@ -0,0 +1,223 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/mutex.h>
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+#include <linux/err.h>
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <bcm63xx_cpu.h>
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+#include <bcm63xx_io.h>
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+#include <bcm63xx_regs.h>
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+#include <bcm63xx_reset.h>
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+
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+#define __GEN_RESET_BITS_TABLE(__cpu) \
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+ [BCM63XX_RESET_SPI] = BCM## __cpu ##_RESET_SPI, \
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+ [BCM63XX_RESET_ENET] = BCM## __cpu ##_RESET_ENET, \
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+ [BCM63XX_RESET_USBH] = BCM## __cpu ##_RESET_USBH, \
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+ [BCM63XX_RESET_USBD] = BCM## __cpu ##_RESET_USBD, \
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+ [BCM63XX_RESET_DSL] = BCM## __cpu ##_RESET_DSL, \
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+ [BCM63XX_RESET_SAR] = BCM## __cpu ##_RESET_SAR, \
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+ [BCM63XX_RESET_EPHY] = BCM## __cpu ##_RESET_EPHY, \
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+ [BCM63XX_RESET_ENETSW] = BCM## __cpu ##_RESET_ENETSW, \
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+ [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
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+ [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
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+ [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
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+ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
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+
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+#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
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+#define BCM6328_RESET_ENET 0
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+#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
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+#define BCM6328_RESET_USBD SOFTRESET_6328_USBS_MASK
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+#define BCM6328_RESET_DSL 0
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+#define BCM6328_RESET_SAR SOFTRESET_6328_SAR_MASK
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+#define BCM6328_RESET_EPHY SOFTRESET_6328_EPHY_MASK
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+#define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
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+#define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
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+#define BCM6328_RESET_MPI 0
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+#define BCM6328_RESET_PCIE \
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+ (SOFTRESET_6328_PCIE_MASK | \
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+ SOFTRESET_6328_PCIE_CORE_MASK | \
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+ SOFTRESET_6328_PCIE_HARD_MASK)
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+#define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
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+
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+#define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
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+#define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
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+#define BCM6338_RESET_USBH SOFTRESET_6338_USBH_MASK
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+#define BCM6338_RESET_USBD SOFTRESET_6338_USBS_MASK
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+#define BCM6338_RESET_DSL SOFTRESET_6338_ADSL_MASK
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+#define BCM6338_RESET_SAR SOFTRESET_6338_SAR_MASK
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+#define BCM6338_RESET_EPHY 0
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+#define BCM6338_RESET_ENETSW 0
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+#define BCM6338_RESET_PCM 0
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+#define BCM6338_RESET_MPI 0
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+#define BCM6338_RESET_PCIE 0
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+#define BCM6338_RESET_PCIE_EXT 0
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+
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+#define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
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+#define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
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+#define BCM6348_RESET_USBH SOFTRESET_6348_USBH_MASK
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+#define BCM6348_RESET_USBD SOFTRESET_6348_USBS_MASK
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+#define BCM6348_RESET_DSL SOFTRESET_6348_ADSL_MASK
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+#define BCM6348_RESET_SAR SOFTRESET_6348_SAR_MASK
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+#define BCM6348_RESET_EPHY 0
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+#define BCM6348_RESET_ENETSW 0
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+#define BCM6348_RESET_PCM 0
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+#define BCM6348_RESET_MPI 0
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+#define BCM6348_RESET_PCIE 0
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+#define BCM6348_RESET_PCIE_EXT 0
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+
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+#define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
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+#define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
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+#define BCM6358_RESET_USBH SOFTRESET_6358_USBH_MASK
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+#define BCM6358_RESET_USBD 0
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+#define BCM6358_RESET_DSL SOFTRESET_6358_ADSL_MASK
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+#define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
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+#define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
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+#define BCM6358_RESET_ENETSW 0
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+#define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
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+#define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
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+#define BCM6358_RESET_PCIE 0
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+#define BCM6358_RESET_PCIE_EXT 0
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+
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+#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
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+#define BCM6368_RESET_ENET 0
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+#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
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+#define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
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+#define BCM6368_RESET_DSL 0
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+#define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
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+#define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
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+#define BCM6368_RESET_ENETSW 0
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+#define BCM6368_RESET_PCM SOFTRESET_6368_PCM_MASK
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+#define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
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+#define BCM6368_RESET_PCIE 0
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+#define BCM6368_RESET_PCIE_EXT 0
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+
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+#ifdef BCMCPU_RUNTIME_DETECT
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+
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+/*
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+ * core reset bits
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+ */
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+static const u32 bcm6328_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6328)
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+};
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+
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+static const u32 bcm6338_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6338)
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+};
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+
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+static const u32 bcm6348_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6348)
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+};
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+
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+static const u32 bcm6358_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6358)
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+};
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+
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+static const u32 bcm6368_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6368)
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+};
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+
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+const u32 *bcm63xx_reset_bits;
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+static int reset_reg;
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+
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+static int __init bcm63xx_reset_bits_init(void)
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+{
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+ if (BCMCPU_IS_6328()) {
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+ reset_reg = PERF_SOFTRESET_6328_REG;
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+ bcm63xx_reset_bits = bcm6328_reset_bits;
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+ } else if (BCMCPU_IS_6338()) {
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+ reset_reg = PERF_SOFTRESET_REG;
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+ bcm63xx_reset_bits = bcm6338_reset_bits;
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+ } else if (BCMCPU_IS_6348()) {
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+ reset_reg = PERF_SOFTRESET_REG;
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+ bcm63xx_reset_bits = bcm6348_reset_bits;
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+ } else if (BCMCPU_IS_6358()) {
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+ reset_reg = PERF_SOFTRESET_6358_REG;
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+ bcm63xx_reset_bits = bcm6358_reset_bits;
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+ } else if (BCMCPU_IS_6368()) {
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+ reset_reg = PERF_SOFTRESET_6368_REG;
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+ bcm63xx_reset_bits = bcm6368_reset_bits;
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+ }
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+
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+ return 0;
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+}
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+#else
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+
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+#ifdef CONFIG_BCM63XX_CPU_6328
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+static const u32 bcm63xx_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6328)
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+};
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+#define reset_reg PERF_SOFTRESET_6328_REG
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+#endif
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+
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+#ifdef CONFIG_BCM63XX_CPU_6338
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+static const u32 bcm63xx_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6338)
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+};
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+#define reset_reg PERF_SOFTRESET_REG
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+#endif
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+
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+#ifdef CONFIG_BCM63XX_CPU_6345
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+static const u32 bcm63xx_reset_bits[] = { };
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+#define reset_reg 0
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+#endif
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+
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+#ifdef CONFIG_BCM63XX_CPU_6348
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+static const u32 bcm63xx_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6348)
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+};
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+#define reset_reg PERF_SOFTRESET_REG
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+#endif
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+
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+#ifdef CONFIG_BCM63XX_CPU_6358
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+static const u32 bcm63xx_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6358)
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+};
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+#define reset_reg PERF_SOFTRESET_6358_REG
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+#endif
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+
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+#ifdef CONFIG_BCM63XX_CPU_6368
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+static const u32 bcm63xx_reset_bits[] = {
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+ __GEN_RESET_BITS_TABLE(6368)
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+};
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+#define reset_reg PERF_SOFTRESET_6368_REG
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+#endif
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+
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+static int __init bcm63xx_reset_bits_init(void) { return 0; }
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+#endif
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+
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+static DEFINE_SPINLOCK(reset_mutex);
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+
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+static void __bcm63xx_core_set_reset(u32 mask, int enable)
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+{
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+ unsigned long flags;
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+ u32 val;
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+
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+ if (!mask)
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+ return;
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+
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+ spin_lock_irqsave(&reset_mutex, flags);
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+ val = bcm_perf_readl(reset_reg);
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+
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+ if (enable)
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+ val &= ~mask;
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+ else
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+ val |= mask;
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+
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+ bcm_perf_writel(val, reset_reg);
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+ spin_unlock_irqrestore(&reset_mutex, flags);
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+}
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+
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+void bcm63xx_core_set_reset(enum bcm63xx_core_reset core, int reset)
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+{
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+ __bcm63xx_core_set_reset(bcm63xx_reset_bits[core], reset);
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+}
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+EXPORT_SYMBOL(bcm63xx_core_set_reset);
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+
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+postcore_initcall(bcm63xx_reset_bits_init);
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
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@@ -0,0 +1,21 @@
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+#ifndef __BCM63XX_RESET_H
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+#define __BCM63XX_RESET_H
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+
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+enum bcm63xx_core_reset {
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+ BCM63XX_RESET_SPI,
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+ BCM63XX_RESET_ENET,
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+ BCM63XX_RESET_USBH,
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+ BCM63XX_RESET_USBD,
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+ BCM63XX_RESET_SAR,
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+ BCM63XX_RESET_DSL,
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+ BCM63XX_RESET_EPHY,
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+ BCM63XX_RESET_ENETSW,
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+ BCM63XX_RESET_PCM,
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+ BCM63XX_RESET_MPI,
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+ BCM63XX_RESET_PCIE,
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+ BCM63XX_RESET_PCIE_EXT,
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+};
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+
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+void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
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+
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+#endif
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