You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
88 lines
3.4 KiB
88 lines
3.4 KiB
From d2ed553484fecdf02fa53bf431599412348afa95 Mon Sep 17 00:00:00 2001
|
|
From: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Date: Thu, 17 Mar 2016 16:22:28 -0500
|
|
Subject: [PATCH 35/37] qcom: ipq4019: add USB nodes to ipq4019 SoC device
|
|
tree
|
|
|
|
This adds the SoC nodes to the ipq4019 device tree
|
|
|
|
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 67 +++++++++++++++++++++++++++++++++++
|
|
1 file changed, 67 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -313,5 +313,72 @@
|
|
compatible = "qcom,pshold";
|
|
reg = <0x4ab000 0x4>;
|
|
};
|
|
+
|
|
+ usb3_ss_phy: ssphy@9a000 {
|
|
+ compatible = "qca,uni-ssphy";
|
|
+ reg = <0x9a000 0x800>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
|
+ reset-names = "por_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3_hs_phy: hsphy@a6000 {
|
|
+ compatible = "qca,baldur-usb3-hsphy";
|
|
+ reg = <0xa6000 0x40>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
|
+ reset-names = "por_rst", "srif_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3@0 {
|
|
+ compatible = "qcom,dwc3";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc GCC_USB3_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@8a00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x8a00000 0xf8000>;
|
|
+ interrupts = <0 132 0>;
|
|
+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ tx-fifo-resize;
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2_hs_phy: hsphy@a8000 {
|
|
+ compatible = "qca,baldur-usb2-hsphy";
|
|
+ reg = <0xa8000 0x40>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
|
+ reset-names = "por_rst", "srif_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2@0 {
|
|
+ compatible = "qcom,dwc3";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc GCC_USB2_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@6000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x6000000 0xf8000>;
|
|
+ interrupts = <0 136 0>;
|
|
+ usb-phy = <&usb2_hs_phy>;
|
|
+ phy-names = "usb2-phy";
|
|
+ tx-fifo-resize;
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|
|
|