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194 lines
4.7 KiB
194 lines
4.7 KiB
--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
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imx6dl-sabresd.dtb \
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imx6dl-wandboard.dtb \
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imx6q-arm2.dtb \
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+ imx6q-gw5400-a.dtb \
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imx6q-sabreauto.dtb \
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imx6q-sabrelite.dtb \
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imx6q-sabresd.dtb \
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--- a/arch/arm/boot/dts/imx6q.dtsi
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+++ b/arch/arm/boot/dts/imx6q.dtsi
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@@ -98,6 +98,14 @@
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MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
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>;
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};
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+
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+ pinctrl_audmux_3: audmux-3 {
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+ fsl,pins = <
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+ MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
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+ MX6Q_PAD_EIM_D25__AUD5_RXC 0x80000000
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+ MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
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+ >;
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+ };
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};
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ecspi1 {
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@@ -187,6 +195,30 @@
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MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
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>;
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};
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+
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+ /* No strobe */
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+ pinctrl_gpmi_nand_2: gpmi-nand-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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+ MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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+ MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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+ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
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+ MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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+ MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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+ MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
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+ MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
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+ MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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+ MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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+ MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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+ MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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+ MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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+ MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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+ MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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+ MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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+ MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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+ MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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+ >;
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+ };
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};
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i2c1 {
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@@ -205,6 +237,12 @@
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MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
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>;
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};
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+ pinctrl_i2c2_2: i2c2grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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+ MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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+ >;
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+ };
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};
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i2c3 {
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@@ -214,6 +252,12 @@
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MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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+ pinctrl_i2c3_2: i2c3grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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+ MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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+ >;
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+ };
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};
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uart1 {
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@@ -223,6 +267,12 @@
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MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
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>;
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};
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+ pinctrl_uart1_2: uart1grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
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+ MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
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+ >;
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+ };
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};
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uart2 {
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@@ -232,6 +282,21 @@
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MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
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>;
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};
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+ pinctrl_uart2_2: uart2grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
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+ MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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+
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+ uart3 {
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+ pinctrl_uart3_1: uart3grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
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+ MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
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+ >;
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+ };
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};
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uart4 {
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@@ -242,6 +307,15 @@
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>;
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};
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};
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+
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+ uart5 {
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+ pinctrl_uart5_1: uart5grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
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+ MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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usbotg {
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pinctrl_usbotg_1: usbotggrp-1 {
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--- a/arch/arm/mach-imx/mach-imx6q.c
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+++ b/arch/arm/mach-imx/mach-imx6q.c
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@@ -25,6 +25,7 @@
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/opp.h>
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+#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/micrel_phy.h>
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@@ -145,6 +146,38 @@ static void __init imx6q_sabrelite_init(
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imx6q_sabrelite_cko1_setup();
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}
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+/*
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+ * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
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+ * as they are used for slots1-7 PERST#
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+ */
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+static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
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+{
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+ u32 dw;
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+
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+ if (!of_machine_is_compatible("gw,ventana"))
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+ return;
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+
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+ if (dev->devfn != 0)
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+ return;
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+
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+ pci_read_config_dword(dev, 0x62c, &dw);
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+ dw |= 0xaaa8; // GPIO1-7 outputs
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+ pci_write_config_dword(dev, 0x62c, dw);
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+
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+ pci_read_config_dword(dev, 0x644, &dw);
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+ dw |= 0xfe; // GPIO1-7 output high
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+ pci_write_config_dword(dev, 0x644, dw);
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+
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+ mdelay(1);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
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+ mx6_ventana_pciesw_early_fixup);
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+
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+static void __init imx6q_ventana_init(void)
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+{
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+ imx6q_sabrelite_cko1_setup();
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+}
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+
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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@@ -163,6 +196,9 @@ static void __init imx6q_usb_init(void)
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static void __init imx6q_init_machine(void)
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{
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+ if (of_machine_is_compatible("gw,ventana"))
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+ imx6q_ventana_init();
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+
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if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
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imx6q_sabrelite_init();
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