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89 lines
3.1 KiB
89 lines
3.1 KiB
From 672d6bea85c7c9c63c086a9423e6d4e5fc286152 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 26 Jun 2013 18:11:56 +0000
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Subject: [PATCH] MIPS: BMIPS: support booting from physical CPU other than 0
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BMIPS43xx CPUs have two hardware threads, and on some SoCs such as 3368,
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the bootloader has configured the system to boot from TP1 instead of the
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more usual TP0. Create the physical to logical CPU mapping to cope with
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that, do not remap the software interrupts to be cross CPUs such that we
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do not have to do use the logical CPU mapping further down the code, and
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finally, reset the slave TP1 only if booted from TP0.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: blogic@openwrt.org
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Cc: cernekee@gmail.com
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Patchwork: https://patchwork.linux-mips.org/patch/5553/
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Patchwork: https://patchwork.linux-mips.org/patch/5556/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/kernel/smp-bmips.c | 29 +++++++++++++++++++++++------
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1 file changed, 23 insertions(+), 6 deletions(-)
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--- a/arch/mips/kernel/smp-bmips.c
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+++ b/arch/mips/kernel/smp-bmips.c
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@@ -63,7 +63,7 @@ static irqreturn_t bmips_ipi_interrupt(i
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static void __init bmips_smp_setup(void)
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{
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- int i;
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+ int i, cpu = 1, boot_cpu = 0;
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#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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/* arbitration priority */
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@@ -72,13 +72,22 @@ static void __init bmips_smp_setup(void)
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/* NBK and weak order flags */
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set_c0_brcm_config_0(0x30000);
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+ /* Find out if we are running on TP0 or TP1 */
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+ boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
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+
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/*
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* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
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* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
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* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
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+ *
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+ * If booting from TP1, leave the existing CMT interrupt routing
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+ * such that TP0 responds to SW1 and TP1 responds to SW0.
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*/
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- change_c0_brcm_cmt_intr(0xf8018000,
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- (0x02 << 27) | (0x03 << 15));
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+ if (boot_cpu == 0)
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+ change_c0_brcm_cmt_intr(0xf8018000,
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+ (0x02 << 27) | (0x03 << 15));
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+ else
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+ change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
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/* single core, 2 threads (2 pipelines) */
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max_cpus = 2;
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@@ -106,9 +115,15 @@ static void __init bmips_smp_setup(void)
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if (!board_ebase_setup)
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board_ebase_setup = &bmips_ebase_setup;
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+ __cpu_number_map[boot_cpu] = 0;
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+ __cpu_logical_map[0] = boot_cpu;
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+
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for (i = 0; i < max_cpus; i++) {
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- __cpu_number_map[i] = 1;
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- __cpu_logical_map[i] = 1;
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+ if (i != boot_cpu) {
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+ __cpu_number_map[i] = cpu;
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+ __cpu_logical_map[cpu] = i;
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+ cpu++;
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+ }
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set_cpu_possible(i, 1);
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set_cpu_present(i, 1);
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}
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@@ -157,7 +172,9 @@ static void bmips_boot_secondary(int cpu
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bmips_send_ipi_single(cpu, 0);
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else {
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#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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- set_c0_brcm_cmt_ctrl(0x01);
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+ /* Reset slave TP1 if booting from TP0 */
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+ if (cpu_logical_map(cpu) == 0)
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+ set_c0_brcm_cmt_ctrl(0x01);
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#elif defined(CONFIG_CPU_BMIPS5000)
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if (cpu & 0x01)
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write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
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