This switch involved:
[1] Regeneration of config (few options went away)
[2] Regeneration of patches so they apply cleanly (different offsets)
[3] Update of .dts files because we now explicitly specify
memory regions in use as opposed to previously used offset
from 0x8000_0000
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 48240
This patch introduces support of new boards with ARC cores.
[1] Synopsys SDP board
This is a new-generation development board from Synopsys that
consists of base-board and CPU tile-board (which might have a real
ASIC or FPGA with CPU image).
It sports a lot of DesignWare peripherals like GMAC, USB, SPI, I2C
etc and is intended to be used for early development of ARC-based
products.
[2] nSIM
This is a virtual board implemented in Synopsys proprietary
software simulator (even though available for free for open source
community). This board has only serial port as a peripheral and so
it is meant to be used for runtime testing which is especially
useful during bring-up of new tools and platforms.
What's also important ARC cores are very configurable so there're
many variations of options like cache sizes, their line lengths,
additional hardware blocks like multipliers, dividers etc. And this
board could be used to make sure built software still runs on
different HW configurations.
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
SVN-Revision: 47589
Felix Fietkau