Updated the devicetree source files to make use of the following
upstreamed drivers:
- xrx200 ethernet phy
- reset controller unit
- dwc2
- fpi
Use our custom xrx200 ethernet phy compatible to support boards, which
have switched the vr9 revision during lifetime, with a single devicetree
source file.
By switching to the dwc2 driver + usb phy framework, we don't need to used
our custom gpio power patch and can use a fixed regulator instead.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Mathias Kresin <dev@kresin.me>
This just copies the patches, configuration and dts files into the
directories hich are used for kernel 4.14.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move the devicetree source files to a kernel specific directory in
preparation of adding kernel 4.14 support.
Rename the subtarget kernel config files to match a specific kernel
version.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Do not disable SPI in the subtarget, otherwise the SPI driver can not
be used.
Disable SPI by default and enable it in the board specific device tree
source file.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This adds USB initialization fixes for Danube, Amazon SE and xrx300 and
should fix the clock on at least Danube which hopefully closes FS#351.
The xrx200 usb driver now uses more memory for the dwc2 fifos, this was
increased in the chip compared to ar9.
This is based in part on the vendor documentation and the vendor code
base as a reference.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use devicetree's /chosen/stdout-path instead of the kernel command line
(embedded in the .dts-files) to specify the serial console. Using the
chosen node is recommended on devicetree based platforms.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
All compiled device tree files not mentioned are binary identical to the
former ones.
Fix the obvious decimal/hex confusion for the power key of ramips/M2M.dts.
Due to the include of the input binding header, the BTN_* node names in:
- ramips/GL-MT300A.dts
- ramips/GL-MT300N.dts
- ramips/GL-MT750.dts
- ramips/Timecloud.dts
will be changed by the compiler to the numerical equivalent.
Move the binding include of lantiq boards to the file where they are
used the first time to hint the user where the values do come from.
Signed-off-by: Mathias Kresin <dev@kresin.me>
- remove not existing properties
- remove properties having the same values as the included dtsi
- remove nodes which are disabled in the included dtsi and not enabled
in dts
- replace the deprecated pinctrl-* compatible strings
- use the same labels for nodes as the included dtsi
- move common used vr9 pci properties to vr9.dtsi
- remove the unused stp node from HomeHub 2B devcie tree source file
- fix spaces vs. tabs and remove superfluous linebreaks
Signed-off-by: Mathias Kresin <dev@kresin.me>
The device tree file of ARV752DPW uses numbers/hex values for gpio states and input event codes.
This cleans it up and uses the available macros from header files. This way the functions are easier to read and comprehend.
Signed-off-by: Andreas Eberlein <foodeas@aeberlein.de>
[sanitize all device tree files]
Signed-off-by: Mathias Kresin <dev@kresin.me>
Compared to the "old" driver:
- Each device must assign a pinctrl setting to the SPI node to allow the
new SPI driver to configure the SPI pins.
While here we are also using separate input and output settings so we
are independent of whether the bootloader configures the pins correctly.
- We use the new "compatible" strings to make the driver choose the
correct number of chip-selects for each SoC.
- The new driver starts counting the chip-selects at 1 (instead of 0, like
the old one did). Thus we have to adjust the devices accordingly.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48293
These were introduced in upstream commit
be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree
bindings" and finally allow us to use the individual pins within our dts
(for example spi_clk, etc.).
Please note that this changes the number of GPIOs which are available for
some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56
pins were exposed. This means that all places which are using hardcoded
GPIO numbers (which are not passed via device-tree) need to be adjusted
(because the first GPIO number is now 462, instead of 456).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48284
Hauke Mehrtens