Gabor Juhos
|
40a5f5c16e
|
ar71xx: define NAND controller base address and register size for AR934X/QCA955x
SVN-Revision: 33382
|
12 years ago |
|
Gabor Juhos
|
2e0e38ad69
|
ar71xx: fix QCA955X_EHCI_SIZE
SVN-Revision: 33360
|
12 years ago |
|
Gabor Juhos
|
94bac7366c
|
ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x
SVN-Revision: 33343
|
12 years ago |
|
Gabor Juhos
|
f4be8a76de
|
ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x
SVN-Revision: 33335
|
12 years ago |
|
Gabor Juhos
|
d1b237b335
|
ar71xx: add initial support for the QCA955X SoCs
SVN-Revision: 32606
|
12 years ago |
|
Gabor Juhos
|
7284cf73d6
|
ar71xx: refactor PCI code to allow registering multiple PCI controllers
SVN-Revision: 32605
|
12 years ago |
|
Gabor Juhos
|
56f2e08537
|
ar71xx: update 3.3 patches
SVN-Revision: 31602
|
13 years ago |
|
Gabor Juhos
|
e9b45ebaba
|
ar71xx: add AR934x specific interface speed setup for ge0
SVN-Revision: 31017
|
13 years ago |
|
Gabor Juhos
|
32a18a05f8
|
ar71xx: add preliminary support for 3.3
SVN-Revision: 30410
|
13 years ago |
|
Gabor Juhos
|
af015f956c
|
ar71xx: add initial support for 3.2
Tested on the following boards:
ALFA AP96
TL-MR3220 v1
TL-WR1043ND v1
TL-WR2543ND v1
TL-WR703N v1
TL-WR741ND v1
TL-WR741ND v4
WNDR3700 v1
WZR-HP-G300NH
SVN-Revision: 29868
|
13 years ago |
