freifunkist-firmware

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Commit Graph

Author	SHA1	Message	Date
Koen Vandeputte	d14aa19904	kernel: bump 4.14 to 4.14.144 Refreshed all patches. Altered patches: - 816-pcie-support-layerscape.patch Fixes: - CVE-2019-15030 Compile-tested on: ar71xx, cns3xxx, imx6, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>	5 years ago
Tomislav Požega	a3c3a8c5ab	ar71xx: enable ddr wb flush on qca955x Enable flushing of write buffers on qca955x. GPL code has 0x88 reg defined for PCI flush which is likely an error since the device freezes on boot. So use DS default value 0xA8 for PCI flush. Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com> (cherry picked from commit fe9e702dc94ece2a004f6db68d6fb9a94d9437cb)	5 years ago

Author

SHA1

Message

Date

Koen Vandeputte

d14aa19904

kernel: bump 4.14 to 4.14.144

Refreshed all patches.

Altered patches:
- 816-pcie-support-layerscape.patch

Fixes:
- CVE-2019-15030

Compile-tested on: ar71xx, cns3xxx, imx6, x86_64
Runtime-tested on: ar71xx, cns3xxx, imx6

Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>

5 years ago

Tomislav Požega

a3c3a8c5ab

ar71xx: enable ddr wb flush on qca955x

Enable flushing of write buffers on qca955x. GPL code has 0x88 reg
defined for PCI flush which is likely an error since the device
freezes on boot. So use DS default value 0xA8 for PCI flush.

Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
(cherry picked from commit fe9e702dc94ece2a004f6db68d6fb9a94d9437cb)

5 years ago

2 Commits (5090152ae3a37482dc1e8290875635305abf12a7)