4 Commits (3572711e3cea24dd5276666860f57a2c3a72525e)

Author	SHA1	Message	Date
Tomasz Maciej Nowak	67ed408af2	mvebu: cortexa9: correct cpu subtype ... Armada 370 processors have only 16 double-precision registers. The change introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for mvebu cortexa9 subtarget to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl> (cherry picked from commit 2d61f8821c7cf99354e904139226c132554ba180)	5 years ago
Tomasz Maciej Nowak	9f6c4ba25c	mvebu: move HARDEN_BRANCH_PREDICTOR to common config ... This symbol is enabled in all subtargets, move it to common kernel config. Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl> Acked-by: Rosen Penev <rosenp@gmail.com>	6 years ago
Koen Vandeputte	ca88f4153f	kernel: bump 4.14 to 4.14.77 ... Refreshed all patches. Altered patches: - 666-Add-support-for-MAP-E-FMRs-mesh-mode.patch New symbol for arm targets: - HARDEN_BRANCH_PREDICTOR Compile-tested on: ar71xx, cns3xxx, imx6 Runtime-tested on: ar71xx, cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>	6 years ago
Hauke Mehrtens	be3da900cd	mvebu: Add subtarget for Cortex A9 build ... This is in preparation for adding a subtarget for the Cortex A53 later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>	7 years ago