- fix single spaces hidden by a tab
- replace indentation with spaces by tabs
- make empty lines empty
- drop trailing whitespace
- drop unnecessary blank lines
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Paul Wassi <p.wassi@gmx.at>
These pins seem to be used by hw exclusively, so claiming it in
kernel causes an error in syslog in k4.14+.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
EA8500 has pcie2 slot unequipped.
By EA8500 hw design default pcie2 reset gpio (gpio63) is used to
reset the switch. That's why enabling pcie2 brings the switch into
a working state.
So let's just control the gpio63 without enabling the pcie2 slot.
We have to remove the pcie2_pins node so the gpio63 is not defined
twice. Because pcie2 node has a reference to pcie2_pins we have to
remove it as well.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
According to OEM bootlog entry mass market devices are ipq8064 SoC
v2.0:
> socinfo_init: v6, id=202, ver=2.0, raw_id=2064, raw_ver=2064, hw_plat=0, hw_plat_ver=65536
I've checked C2600, EA8500 and VR2600v but couldn't find other
boards bootlog. I think it's safe to assume that other boards are
also v2.0. R7500 may be an exception because it was the first
device to hit the market.
So switch to v2.0 dtsi.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
- Rebased the patches for 4.14
- Dropped spi-qup and 0027, 0028, 0029
clk patches since it's already included
in upstream.
Tested on IPQ AP148 Board:
1) NOR boot and NAND boot
2) Tested USB and PCIe interfaces
3) WDOG test
4) cpu frequency scaling
5) ethernet, 2G and 5G WiFi
6) ubi sysupgrade
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode.
EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode.
In previous commit we've added the support for this option, so enable it in DT for affected devices.
QSDK ref:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506
While at it move the phy transmit termination offset value into dtsi file as it's platform specific.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Set the pinmux to the values found in the GPL tarballs of the boards.
Remove pinmux which are is not used (like nand pinmux for spi
flash boards).
This allows to use the wan orange led of the C2600 which had a wrong
pinmux before. Might fix buttons or leds of other boards as well.
Fix the LED color and the ledswitch key code of the C2600. Rename the
ledgnr to ledswitch.
Add support for indication the boot state using LEDs to the D7800,
NBG6817, R7500 and R7500v2.
Change GPIO active to readable values in D7800, EA8500, R7500,
R7500v2 and R7800.
Change gpioexport to gpio pinmux.
Add proper "drive strenght" to i2c4_pins and use it for RPM on
C2600, D7800, EA8500, R7500, R7500v2.
Remove pcie pinmux from D7800.
Move pinctrl to correct place in NBG6817 and R7800.
Signed-off-by: Henryk Heisig <hyniu@o2.pl>
The command-line arguments provided by the boot loader will be
appended to a new device tree property: bootloader-args.
If there is a property "append-rootblock" in DT under /chosen
and a root= option in bootloaders command line it will be parsed
and added to DT bootargs with the form: <append-rootblock>XX.
Only command line ATAG will be processed, the rest of the ATAGs
sent by bootloader will be ignored.
This is usefull in dual boot systems, to get the current root partition
without afecting the rest of the system.
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
Paul Wassi