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@ -2,6 +2,7 @@ |
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* ar8216.c: AR8216 switch driver |
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* |
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* Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> |
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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@ -30,6 +31,7 @@ |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/lockdep.h> |
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#include <linux/ar8216_platform.h> |
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#include "ar8216.h" |
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/* size of the vlan table */ |
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@ -70,6 +72,7 @@ struct ar8216_priv { |
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char buf[80]; |
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bool init; |
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bool mii_lo_first; |
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/* all fields below are cleared on reset */ |
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bool vlan; |
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@ -137,8 +140,13 @@ ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val) |
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bus->write(bus, 0x18, 0, r3); |
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usleep_range(1000, 2000); /* wait for the page switch to propagate */ |
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bus->write(bus, 0x10 | r2, r1 + 1, hi); |
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bus->write(bus, 0x10 | r2, r1, lo); |
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if (priv->mii_lo_first) { |
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bus->write(bus, 0x10 | r2, r1, lo); |
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bus->write(bus, 0x10 | r2, r1 + 1, hi); |
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} else { |
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bus->write(bus, 0x10 | r2, r1 + 1, hi); |
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bus->write(bus, 0x10 | r2, r1, lo); |
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} |
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mutex_unlock(&bus->mdio_lock); |
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} |
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@ -609,6 +617,309 @@ static const struct ar8xxx_chip ar8316_chip = { |
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.vtu_load_vlan = ar8216_vtu_load_vlan, |
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}; |
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static u32 |
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ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) |
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{ |
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u32 t; |
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if (!cfg) |
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return 0; |
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t = 0; |
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switch (cfg->mode) { |
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case AR8327_PAD_NC: |
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break; |
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case AR8327_PAD_MAC2MAC_MII: |
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t = AR8327_PAD_MAC_MII_EN; |
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if (cfg->rxclk_sel) |
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t |= AR8327_PAD_MAC_MII_RXCLK_SEL; |
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if (cfg->txclk_sel) |
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t |= AR8327_PAD_MAC_MII_TXCLK_SEL; |
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break; |
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case AR8327_PAD_MAC2MAC_GMII: |
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t = AR8327_PAD_MAC_GMII_EN; |
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if (cfg->rxclk_sel) |
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t |= AR8327_PAD_MAC_GMII_RXCLK_SEL; |
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if (cfg->txclk_sel) |
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t |= AR8327_PAD_MAC_GMII_TXCLK_SEL; |
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break; |
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case AR8327_PAD_MAC_SGMII: |
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t = AR8327_PAD_SGMII_EN; |
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break; |
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case AR8327_PAD_MAC2PHY_MII: |
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t = AR8327_PAD_PHY_MII_EN; |
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if (cfg->rxclk_sel) |
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t |= AR8327_PAD_PHY_MII_RXCLK_SEL; |
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if (cfg->txclk_sel) |
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t |= AR8327_PAD_PHY_MII_TXCLK_SEL; |
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break; |
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case AR8327_PAD_MAC2PHY_GMII: |
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t = AR8327_PAD_PHY_GMII_EN; |
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if (cfg->pipe_rxclk_sel) |
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t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL; |
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if (cfg->rxclk_sel) |
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t |= AR8327_PAD_PHY_GMII_RXCLK_SEL; |
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if (cfg->txclk_sel) |
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t |= AR8327_PAD_PHY_GMII_TXCLK_SEL; |
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break; |
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case AR8327_PAD_MAC_RGMII: |
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t = AR8327_PAD_RGMII_EN; |
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t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; |
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t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; |
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if (cfg->rxclk_delay_en) |
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t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; |
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if (cfg->txclk_delay_en) |
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t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; |
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break; |
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case AR8327_PAD_PHY_GMII: |
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t = AR8327_PAD_PHYX_GMII_EN; |
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break; |
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case AR8327_PAD_PHY_RGMII: |
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t = AR8327_PAD_PHYX_RGMII_EN; |
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break; |
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case AR8327_PAD_PHY_MII: |
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t = AR8327_PAD_PHYX_MII_EN; |
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break; |
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} |
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return t; |
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} |
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static int |
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ar8327_hw_init(struct ar8216_priv *priv) |
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{ |
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struct ar8327_platform_data *pdata; |
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u32 t; |
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int i; |
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pdata = priv->phy->dev.platform_data; |
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if (!pdata) |
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return -EINVAL; |
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t = ar8327_get_pad_cfg(pdata->pad0_cfg); |
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priv->write(priv, AR8327_REG_PAD0_MODE, t); |
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t = ar8327_get_pad_cfg(pdata->pad5_cfg); |
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priv->write(priv, AR8327_REG_PAD5_MODE, t); |
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t = ar8327_get_pad_cfg(pdata->pad6_cfg); |
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priv->write(priv, AR8327_REG_PAD6_MODE, t); |
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priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000); |
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/* fixup PHYs */ |
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for (i = 0; i < AR8327_NUM_PHYS; i++) { |
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/* For 100M waveform */ |
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ar8216_phy_dbg_write(priv, i, 0, 0x02ea); |
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/* Turn on Gigabit clock */ |
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ar8216_phy_dbg_write(priv, i, 0x3d, 0x68a0); |
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} |
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return 0; |
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} |
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static void |
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ar8327_init_globals(struct ar8216_priv *priv) |
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{ |
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u32 t; |
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/* enable CPU port and disable mirror port */ |
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t = AR8327_FWD_CTRL0_CPU_PORT_EN | |
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AR8327_FWD_CTRL0_MIRROR_PORT; |
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priv->write(priv, AR8327_REG_FWD_CTRL0, t); |
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/* forward multicast and broadcast frames to CPU */ |
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t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) | |
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(AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S); |
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priv->write(priv, AR8327_REG_FWD_CTRL1, t); |
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/* setup MTU */ |
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ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE, |
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AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2); |
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} |
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static void |
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ar8327_init_cpuport(struct ar8216_priv *priv) |
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{ |
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struct ar8327_platform_data *pdata; |
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struct ar8327_port_cfg *cfg; |
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u32 t; |
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pdata = priv->phy->dev.platform_data; |
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if (!pdata) |
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return; |
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cfg = &pdata->cpuport_cfg; |
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if (!cfg->force_link) { |
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priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), |
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AR8216_PORT_STATUS_LINK_AUTO); |
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return; |
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} |
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t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC; |
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t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0; |
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t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0; |
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t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0; |
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switch (cfg->speed) { |
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case AR8327_PORT_SPEED_10: |
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t |= AR8216_PORT_SPEED_10M; |
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break; |
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case AR8327_PORT_SPEED_100: |
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t |= AR8216_PORT_SPEED_100M; |
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break; |
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case AR8327_PORT_SPEED_1000: |
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t |= AR8216_PORT_SPEED_1000M; |
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break; |
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} |
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priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t); |
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} |
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static void |
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ar8327_init_port(struct ar8216_priv *priv, int port) |
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{ |
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u32 t; |
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if (port == AR8216_PORT_CPU) { |
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ar8327_init_cpuport(priv); |
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} else { |
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t = AR8216_PORT_STATUS_LINK_AUTO; |
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priv->write(priv, AR8327_REG_PORT_STATUS(port), t); |
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} |
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priv->write(priv, AR8327_REG_PORT_HEADER(port), 0); |
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priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0); |
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t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S; |
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priv->write(priv, AR8327_REG_PORT_VLAN1(port), t); |
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t = AR8327_PORT_LOOKUP_LEARN; |
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t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; |
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priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t); |
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} |
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static u32 |
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ar8327_read_port_status(struct ar8216_priv *priv, int port) |
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{ |
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return priv->read(priv, AR8327_REG_PORT_STATUS(port)); |
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} |
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static int |
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ar8327_atu_flush(struct ar8216_priv *priv) |
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{ |
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int ret; |
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ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC, |
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AR8327_ATU_FUNC_BUSY, 0); |
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if (!ret) |
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priv->write(priv, AR8327_REG_ATU_FUNC, |
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AR8327_ATU_FUNC_OP_FLUSH); |
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return ret; |
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} |
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static void |
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ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val) |
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{ |
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if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1, |
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AR8327_VTU_FUNC1_BUSY, 0)) |
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return; |
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if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) |
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priv->write(priv, AR8327_REG_VTU_FUNC0, val); |
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op |= AR8327_VTU_FUNC1_BUSY; |
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priv->write(priv, AR8327_REG_VTU_FUNC1, op); |
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} |
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static void |
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ar8327_vtu_flush(struct ar8216_priv *priv) |
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{ |
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ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0); |
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} |
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static void |
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ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask) |
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{ |
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u32 op; |
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u32 val; |
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int i; |
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op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S); |
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val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL; |
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for (i = 0; i < AR8327_NUM_PORTS; i++) { |
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u32 mode; |
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if ((port_mask & BIT(i)) == 0) |
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mode = AR8327_VTU_FUNC0_EG_MODE_NOT; |
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else if (priv->vlan == 0) |
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mode = AR8327_VTU_FUNC0_EG_MODE_KEEP; |
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else if (priv->vlan_tagged & BIT(i)) |
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mode = AR8327_VTU_FUNC0_EG_MODE_TAG; |
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else |
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mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG; |
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val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i); |
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} |
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ar8327_vtu_op(priv, op, val); |
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} |
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static void |
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ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress, |
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u32 members, u32 pvid) |
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{ |
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u32 t; |
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u32 mode; |
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t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S; |
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t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S; |
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priv->write(priv, AR8327_REG_PORT_VLAN0(port), t); |
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mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD; |
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switch (egress) { |
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case AR8216_OUT_KEEP: |
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mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; |
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break; |
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case AR8216_OUT_STRIP_VLAN: |
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mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG; |
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break; |
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case AR8216_OUT_ADD_VLAN: |
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mode = AR8327_PORT_VLAN1_OUT_MODE_TAG; |
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break; |
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} |
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t = AR8327_PORT_VLAN1_PORT_VLAN_PROP; |
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t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S; |
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priv->write(priv, AR8327_REG_PORT_VLAN1(port), t); |
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t = members; |
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t |= AR8327_PORT_LOOKUP_LEARN; |
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t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S; |
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t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; |
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priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t); |
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} |
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static const struct ar8xxx_chip ar8327_chip = { |
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.caps = AR8XXX_CAP_GIGE, |
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.hw_init = ar8327_hw_init, |
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.init_globals = ar8327_init_globals, |
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.init_port = ar8327_init_port, |
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.setup_port = ar8327_setup_port, |
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.read_port_status = ar8327_read_port_status, |
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.atu_flush = ar8327_atu_flush, |
|
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.vtu_flush = ar8327_vtu_flush, |
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|
.vtu_load_vlan = ar8327_vtu_load_vlan, |
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|
}; |
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|
|
|
|
|
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|
static int |
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|
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ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, |
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|
struct switch_val *val) |
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@ -910,6 +1221,11 @@ ar8216_id_chip(struct ar8216_priv *priv) |
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priv->chip_type = AR8316; |
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priv->chip = &ar8316_chip; |
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|
break; |
|
|
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|
case 0x1202: |
|
|
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|
priv->chip_type = AR8327; |
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|
|
|
priv->mii_lo_first = true; |
|
|
|
|
priv->chip = &ar8327_chip; |
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|
|
|
break; |
|
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|
|
default: |
|
|
|
|
printk(KERN_DEBUG |
|
|
|
|
"ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n", |
|
|
|
@ -1012,6 +1328,10 @@ ar8216_config_init(struct phy_device *pdev) |
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|
|
swdev->name = "Atheros AR8236"; |
|
|
|
|
swdev->vlans = AR8216_NUM_VLANS; |
|
|
|
|
swdev->ports = AR8216_NUM_PORTS; |
|
|
|
|
} else if (priv->chip_type == AR8327) { |
|
|
|
|
swdev->name = "Atheros AR8327"; |
|
|
|
|
swdev->vlans = AR8X16_MAX_VLANS; |
|
|
|
|
swdev->ports = AR8327_NUM_PORTS; |
|
|
|
|
} else { |
|
|
|
|
swdev->name = "Atheros AR8216"; |
|
|
|
|
swdev->vlans = AR8216_NUM_VLANS; |
|
|
|
|