Backport below changes for GigaDevice GD25Q256 support from v4.15: e27072851bf7 mtd: spi-nor: add a quad_enable callback in struct flash_info 65153846b18c mtd: spi-nor: add support for GD25Q256 This chip is used on newer Quad-E4G boards. Before: [ 2.366493] m25p80 spi0.0: unrecognized JEDEC id bytes: c8, 40, 19 [ 2.372853] m25p80: probe of spi0.0 failed with error -2 After: [ 2.371722] m25p80 spi0.0: gd25q256 (32768 Kbytes) [ 2.376694] 5 fixed-partitions partitions found on MTD device spi0.0 [ 2.383043] Creating 5 MTD partitions on "spi0.0": [ 2.387824] 0x000000000000-0x000000030000 : "u-boot" [ 2.394138] 0x000000030000-0x000000031000 : "u-boot-env" [ 2.400608] 0x000000031000-0x000000040000 : "config" [ 2.406830] 0x000000040000-0x000000050000 : "factory" [ 2.413169] 0x000000050000-0x000002000000 : "firmware" Signed-off-by: Kuan-Yi Li <kyli@abysm.org>master
Kuan-Yi Li
4 years ago
committed by
Hauke Mehrtens
parent
c72b7a4f0d
commit
f1525e785e
@ -0,0 +1,47 @@ |
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From e27072851bf7d706c592fc528549b52023b17a09 Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Mon, 28 Aug 2017 09:58:29 +0800
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Subject: [PATCH 1/2] mtd: spi-nor: add a quad_enable callback in struct
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flash_info
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Some manufacturers may use different bit to set QE on different
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memories.
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The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
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of the Status Register-1) to set QE, which is different with
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other supported memories from GigaDevice that use S9(bit 1 of
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the Status Register-2). This makes it is impossible to select
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the quad enable method by distinguishing the MFR. This patch
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introduce a quad_enable function which can be set per memory
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in the flash_info list table.
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -89,6 +89,8 @@ struct flash_info {
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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+
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+ int (*quad_enable)(struct spi_nor *nor);
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@@ -2433,6 +2435,15 @@ static int spi_nor_init_params(struct sp
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params->quad_enable = spansion_quad_enable;
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break;
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}
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+
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+ /*
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+ * Some manufacturer like GigaDevice may use different
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+ * bit to set QE on different memories, so the MFR can't
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+ * indicate the quad_enable method for this case, we need
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+ * set it in flash info list.
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+ */
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+ if (info->quad_enable)
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+ params->quad_enable = info->quad_enable;
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}
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/* Override the parameters with data read from SFDP tables. */
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@ -0,0 +1,35 @@ |
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From 65153846b18c486ce3c90477c467d53915114e3f Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Mon, 28 Aug 2017 10:00:46 +0800
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Subject: [PATCH 2/2] mtd: spi-nor: add support for GD25Q256
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Add support for GD25Q256, a 32MiB SPI Nor flash
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from GigaDevice.
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_
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return ret;
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}
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+static int macronix_quad_enable(struct spi_nor *nor);
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+
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/* Used when the "_ext_id" is two bytes at most */
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#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_i
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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+ {
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+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ .quad_enable = macronix_quad_enable,
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+ },
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/* Intel/Numonyx -- xxxs33b */
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{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
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