Florian Fainelli
18 years ago
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56d10f7c3c
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ef53f5db7c
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/*
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* $Id$ |
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* |
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* ADM5120 SoC definitions |
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* |
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* This file defines some constants specific to the ADM5120 SoC |
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* |
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* Copyright (C) 2007 OpenWrt.org |
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version 2 |
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* of the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the |
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, |
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* Boston, MA 02110-1301, USA. |
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*/ |
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#ifndef _ADM5120_DEFS_H |
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#define _ADM5120_DEFS_H |
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#define ADM5120_SDRAM0_BASE 0x00000000 |
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#define ADM5120_SDRAM1_BASE 0x01000000 |
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#define ADM5120_SRAM1_BASE 0x10000000 |
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#define ADM5120_MPMC_BASE 0x11000000 |
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#define ADM5120_USBC_BASE 0x11200000 |
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#define ADM5120_PCIMEM_BASE 0x11400000 |
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#define ADM5120_PCIIO_BASE 0x11500000 |
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#define ADM5120_PCICFG_ADDR 0x115FFFF0 |
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#define ADM5120_PCICFG_DATA 0x115FFFF8 |
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#define ADM5120_SWITCH_BASE 0x12000000 |
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#define ADM5120_INTC_BASE 0x12200000 |
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#define ADM5120_UART0_BASE 0x12600000 |
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#define ADM5120_UART1_BASE 0x12800000 |
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#define ADM5120_SRAM0_BASE 0x1FC00000 |
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#define ADM5120_MPMC_SIZE 0x1000 |
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#define ADM5120_USBC_SIZE 0x84 |
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#define ADM5120_PCIMEM_SIZE (ADM5120_PCIIO_BASE - ADM5120_PCIMEM_BASE) |
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#define ADM5120_PCIIO_SIZE (ADM5120_PCICFG_ADDR - ADM5120_PCIIO_BASE) |
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#define ADM5120_PCICFG_SIZE 0x10 |
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#define ADM5120_SWITCH_SIZE 0x114 |
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#define ADM5120_INTC_SIZE 0x28 |
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#define ADM5120_UART_SIZE 0x20 |
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#define ADM5120_CLK_175 175000000 |
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#define ADM5120_CLK_200 200000000 |
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#define ADM5120_CLK_225 225000000 |
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#define ADM5120_CLK_250 250000000 |
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#define ADM5120_UART_CLOCK 62500000 |
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#endif /* _ADM5120_DEFS_H */ |
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@ -0,0 +1,89 @@ |
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/*
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* ADM5120 ethernet switch definitions |
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* |
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* This header file defines the hardware registers of the ADM5120 SoC |
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* built-in Ethernet switch. |
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* |
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* Copyright (C) 2007 OpenWrt.org |
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version 2 |
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* of the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the |
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, |
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* Boston, MA 02110-1301, USA. |
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*/ |
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#ifndef _ADM5120_SWITCH_H |
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#define _ADM5120_SWITCH_H |
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#define BITMASK(len) ((1 << (len))-1) |
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#define ONEBIT(at) (1 << (at)) |
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/* Switch register offsets */ |
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#define SWITCH_REG_CODE 0x0000 |
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#define SWITCH_REG_SOFT_RESET 0x0004 |
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#define SWITCH_REG_MEMCTRL 0x001C |
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#define SWITCH_REG_CPUP_CONF 0x0024 |
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#define SWITCH_REG_PORT_CONF0 0x0028 |
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#define SWITCH_REG_PORT_CONF1 0x002C |
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#define SWITCH_REG_PORT_CONF2 0x0030 |
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#define SWITCH_REG_VLAN_G1 0x0040 |
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#define SWITCH_REG_VLAN_G2 0x0044 |
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#define SWITCH_REG_SEND_TRIG 0x0048 |
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#define SWITCH_REG_MAC_WT0 0x0058 |
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#define SWITCH_REG_MAC_WT1 0x005C |
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#define SWITCH_REG_PHY_CNTL0 0x0068 |
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#define SWITCH_REG_PHY_CNTL1 0x006C |
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#define SWITCH_REG_PHY_CNTL2 0x007C |
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#define SWITCH_REG_PHY_CNTL3 0x0080 |
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#define SWITCH_REG_PRI_CNTL 0x0084 |
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#define SWITCH_REG_INT_STATUS 0x00B0 |
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#define SWITCH_REG_INT_MASK 0x00B4 |
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#define SWITCH_REG_GPIO_CONF0 0x00B8 |
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#define SWITCH_REG_GPIO_CONF2 0x00BC |
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#define SWITCH_REG_WDOG0 0x00C0 |
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#define SWITCH_REG_WDOG1 0x00C4 |
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#define SWITCH_REG_PHY_CNTL4 0x00A0 |
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#define SWITCH_REG_SEND_HBADDR 0x00D0 |
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#define SWITCH_REG_SEND_LBADDR 0x00D4 |
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#define SWITCH_REG_RECV_HBADDR 0x00D8 |
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#define SWITCH_REG_RECV_LBADDR 0x00DC |
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#define SWITCH_REG_TIMER_INT 0x00F0 |
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#define SWITCH_REG_TIMER 0x00F4 |
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#define SWITCH_REG_PORT0_LED 0x0100 |
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#define SWITCH_REG_PORT1_LED 0x0104 |
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#define SWITCH_REG_PORT2_LED 0x0108 |
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#define SWITCH_REG_PORT3_LED 0x010C |
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#define SWITCH_REG_PORT4_LED 0x0110 |
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/* CODE register bits */ |
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#define CODE_PC_MASK BITMASK(16) /* Product Code */ |
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#define CODE_REV_SHIFT 16 |
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#define CODE_REV_MASK BITMASK(4) /* Product Revision */ |
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#define CODE_CLKS_SHIFT 20 |
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#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */ |
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#define CODE_CLKS_175 0 /* 175 MHz */ |
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#define CODE_CLKS_200 1 /* 200 MHz */ |
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#define CODE_CLKS_225 2 /* 225 MHz */ |
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#define CODE_CLKS_250 3 /* 250 MHz */ |
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#define CODE_NAB ONEBIT(24) /* NAND boot */ |
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#define CODE_PK_MASK BITMASK(1) /* Package type */ |
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#define CODE_PK_SHIFT 29 |
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#define CODE_PK_BGA 0 /* BGA package */ |
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#define CODE_PK_PQFP 1 /* PQFP package */ |
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#endif /* _ADM5120_SWITCH_H */ |
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