The previous round of fixes for the 82574 chip cause an issue with emulated e1000e devices in VMware ESXi 6.5. It also contains changes that are not strictly necessary. These patches fix the issues introduced in the previous series, revert the unnecessary changes to avoid unforeseen fallout, and avoid a case where interrupts can be missed. The final two patches of this series are already in the kernel, so no need to include them here. Patchwork: https://patchwork.ozlabs.org/cover/881776/ Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>master
Stijn Tintel
6 years ago
parent
22b9f99b87
commit
ef025e6417
@ -0,0 +1,66 @@ |
||||
From patchwork Mon Mar 5 21:40:25 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [net,v2,1/6] e1000e: Remove Other from EIAC
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X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
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X-Patchwork-Id: 881773
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X-Patchwork-Delegate: davem@davemloft.net
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Message-Id: <20180305214030.25141-2-jeffrey.t.kirsher@intel.com>
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To: davem@davemloft.net
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Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
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nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
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Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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Date: Mon, 5 Mar 2018 13:40:25 -0800
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From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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List-Id: <netdev.vger.kernel.org>
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From: Benjamin Poirier <bpoirier@suse.com>
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It was reported that emulated e1000e devices in vmware esxi 6.5 Build
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7526125 do not link up after commit 4aea7a5c5e94 ("e1000e: Avoid receiver
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overrun interrupt bursts", v4.15-rc1). Some tracing shows that after
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e1000e_trigger_lsc() is called, ICR reads out as 0x0 in e1000_msix_other()
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on emulated e1000e devices. In comparison, on real e1000e 82574 hardware,
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icr=0x80000004 (_INT_ASSERTED | _LSC) in the same situation.
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Some experimentation showed that this flaw in vmware e1000e emulation can
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be worked around by not setting Other in EIAC. This is how it was before
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16ecba59bc33 ("e1000e: Do not read ICR in Other interrupt", v4.5-rc1).
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Fixes: 4aea7a5c5e94 ("e1000e: Avoid receiver overrun interrupt bursts")
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Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
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Tested-by: Aaron Brown <aaron.f.brown@intel.com>
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Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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---
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drivers/net/ethernet/intel/e1000e/netdev.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/net/ethernet/intel/e1000e/netdev.c
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+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
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@@ -1914,6 +1914,8 @@ static irqreturn_t e1000_msix_other(int
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bool enable = true;
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icr = er32(ICR);
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+ ew32(ICR, E1000_ICR_OTHER);
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+
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if (icr & E1000_ICR_RXO) {
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ew32(ICR, E1000_ICR_RXO);
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enable = false;
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@@ -2036,7 +2038,6 @@ static void e1000_configure_msix(struct
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hw->hw_addr + E1000_EITR_82574(vector));
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else
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writel(1, hw->hw_addr + E1000_EITR_82574(vector));
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- adapter->eiac_mask |= E1000_IMS_OTHER;
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/* Cause Tx interrupts on every write back */
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ivar |= BIT(31);
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@@ -2261,7 +2262,7 @@ static void e1000_irq_enable(struct e100
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if (adapter->msix_entries) {
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ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
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- ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC);
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+ ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
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} else if (hw->mac.type >= e1000_pch_lpt) {
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ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
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} else {
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@ -0,0 +1,84 @@ |
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From patchwork Mon Mar 5 21:40:26 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [net, v2,
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2/6] Partial revert "e1000e: Avoid receiver overrun interrupt bursts"
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X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
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X-Patchwork-Id: 881769
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X-Patchwork-Delegate: davem@davemloft.net
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Message-Id: <20180305214030.25141-3-jeffrey.t.kirsher@intel.com>
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To: davem@davemloft.net
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Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
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nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
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Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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Date: Mon, 5 Mar 2018 13:40:26 -0800
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From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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List-Id: <netdev.vger.kernel.org>
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From: Benjamin Poirier <bpoirier@suse.com>
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This partially reverts commit 4aea7a5c5e940c1723add439f4088844cd26196d.
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We keep the fix for the first part of the problem (1) described in the log
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of that commit, that is to read ICR in the other interrupt handler. We
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remove the fix for the second part of the problem (2), Other interrupt
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throttling.
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Bursts of "Other" interrupts may once again occur during rxo (receive
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overflow) traffic conditions. This is deemed acceptable in the interest of
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avoiding unforeseen fallout from changes that are not strictly necessary.
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As discussed, the e1000e driver should be in "maintenance mode".
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Link: https://www.spinics.net/lists/netdev/msg480675.html
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Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
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Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
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Tested-by: Aaron Brown <aaron.f.brown@intel.com>
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Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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---
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drivers/net/ethernet/intel/e1000e/netdev.c | 16 ++--------------
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1 file changed, 2 insertions(+), 14 deletions(-)
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--- a/drivers/net/ethernet/intel/e1000e/netdev.c
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+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
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@@ -1911,21 +1911,10 @@ static irqreturn_t e1000_msix_other(int
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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u32 icr;
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- bool enable = true;
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icr = er32(ICR);
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ew32(ICR, E1000_ICR_OTHER);
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- if (icr & E1000_ICR_RXO) {
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- ew32(ICR, E1000_ICR_RXO);
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- enable = false;
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- /* napi poll will re-enable Other, make sure it runs */
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- if (napi_schedule_prep(&adapter->napi)) {
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- adapter->total_rx_bytes = 0;
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- adapter->total_rx_packets = 0;
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- __napi_schedule(&adapter->napi);
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- }
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- }
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if (icr & E1000_ICR_LSC) {
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ew32(ICR, E1000_ICR_LSC);
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hw->mac.get_link_status = true;
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@@ -1934,7 +1923,7 @@ static irqreturn_t e1000_msix_other(int
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mod_timer(&adapter->watchdog_timer, jiffies + 1);
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}
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- if (enable && !test_bit(__E1000_DOWN, &adapter->state))
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+ if (!test_bit(__E1000_DOWN, &adapter->state))
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ew32(IMS, E1000_IMS_OTHER);
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return IRQ_HANDLED;
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@@ -2704,8 +2693,7 @@ static int e1000e_poll(struct napi_struc
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napi_complete_done(napi, work_done);
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if (!test_bit(__E1000_DOWN, &adapter->state)) {
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if (adapter->msix_entries)
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- ew32(IMS, adapter->rx_ring->ims_val |
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- E1000_IMS_OTHER);
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+ ew32(IMS, adapter->rx_ring->ims_val);
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else
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e1000_irq_enable(adapter);
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}
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@ -0,0 +1,50 @@ |
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From patchwork Mon Mar 5 21:40:27 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [net, v2,
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3/6] e1000e: Fix queue interrupt re-raising in Other interrupt
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X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
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X-Patchwork-Id: 881775
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X-Patchwork-Delegate: davem@davemloft.net
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Message-Id: <20180305214030.25141-4-jeffrey.t.kirsher@intel.com>
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To: davem@davemloft.net
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Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
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nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
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Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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Date: Mon, 5 Mar 2018 13:40:27 -0800
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From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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List-Id: <netdev.vger.kernel.org>
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From: Benjamin Poirier <bpoirier@suse.com>
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Restores the ICS write for Rx/Tx queue interrupts which was present before
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commit 16ecba59bc33 ("e1000e: Do not read ICR in Other interrupt", v4.5-rc1)
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but was not restored in commit 4aea7a5c5e94
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("e1000e: Avoid receiver overrun interrupt bursts", v4.15-rc1).
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This re-raises the queue interrupts in case the txq or rxq bits were set in
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ICR and the Other interrupt handler read and cleared ICR before the queue
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interrupt was raised.
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Fixes: 4aea7a5c5e94 ("e1000e: Avoid receiver overrun interrupt bursts")
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Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
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Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
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Tested-by: Aaron Brown <aaron.f.brown@intel.com>
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Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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---
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drivers/net/ethernet/intel/e1000e/netdev.c | 3 +++
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1 file changed, 3 insertions(+)
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--- a/drivers/net/ethernet/intel/e1000e/netdev.c
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+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
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@@ -1915,6 +1915,9 @@ static irqreturn_t e1000_msix_other(int
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icr = er32(ICR);
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ew32(ICR, E1000_ICR_OTHER);
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+ if (icr & adapter->eiac_mask)
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+ ew32(ICS, (icr & adapter->eiac_mask));
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+
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if (icr & E1000_ICR_LSC) {
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ew32(ICR, E1000_ICR_LSC);
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hw->mac.get_link_status = true;
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@ -0,0 +1,131 @@ |
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From patchwork Mon Mar 5 21:40:28 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [net,v2,4/6] e1000e: Avoid missed interrupts following ICR read
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X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
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X-Patchwork-Id: 881771
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X-Patchwork-Delegate: davem@davemloft.net
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Message-Id: <20180305214030.25141-5-jeffrey.t.kirsher@intel.com>
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To: davem@davemloft.net
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Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
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nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
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Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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Date: Mon, 5 Mar 2018 13:40:28 -0800
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From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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List-Id: <netdev.vger.kernel.org>
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From: Benjamin Poirier <bpoirier@suse.com>
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The 82574 specification update errata 12 states that interrupts may be
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missed if ICR is read while INT_ASSERTED is not set. Avoid that problem by
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setting all bits related to events that can trigger the Other interrupt in
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IMS.
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The Other interrupt is raised for such events regardless of whether or not
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they are set in IMS. However, only when they are set is the INT_ASSERTED
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bit also set in ICR.
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By doing this, we ensure that INT_ASSERTED is always set when we read ICR
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in e1000_msix_other() and steer clear of the errata. This also ensures that
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ICR will automatically be cleared on read, therefore we no longer need to
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clear bits explicitly.
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Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
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Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
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Tested-by: Aaron Brown <aaron.f.brown@intel.com>
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Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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---
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drivers/net/ethernet/intel/e1000e/defines.h | 21 ++++++++++++++++++++-
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drivers/net/ethernet/intel/e1000e/netdev.c | 11 ++++-------
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2 files changed, 24 insertions(+), 8 deletions(-)
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--- a/drivers/net/ethernet/intel/e1000e/defines.h
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+++ b/drivers/net/ethernet/intel/e1000e/defines.h
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@@ -400,6 +400,10 @@
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#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
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#define E1000_ICR_RXO 0x00000040 /* Receiver Overrun */
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#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
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+#define E1000_ICR_MDAC 0x00000200 /* MDIO Access Complete */
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+#define E1000_ICR_SRPD 0x00010000 /* Small Receive Packet Detected */
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+#define E1000_ICR_ACK 0x00020000 /* Receive ACK Frame Detected */
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+#define E1000_ICR_MNG 0x00040000 /* Manageability Event Detected */
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#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
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/* If this bit asserted, the driver should claim the interrupt */
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#define E1000_ICR_INT_ASSERTED 0x80000000
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@@ -407,7 +411,7 @@
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#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
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#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
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#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
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-#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
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+#define E1000_ICR_OTHER 0x01000000 /* Other Interrupt */
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/* PBA ECC Register */
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#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
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@@ -431,12 +435,27 @@
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E1000_IMS_RXSEQ | \
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E1000_IMS_LSC)
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+/* These are all of the events related to the OTHER interrupt.
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+ */
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+#define IMS_OTHER_MASK ( \
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+ E1000_IMS_LSC | \
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+ E1000_IMS_RXO | \
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+ E1000_IMS_MDAC | \
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+ E1000_IMS_SRPD | \
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+ E1000_IMS_ACK | \
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+ E1000_IMS_MNG)
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+
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/* Interrupt Mask Set */
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#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
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#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
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#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
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#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
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+#define E1000_IMS_RXO E1000_ICR_RXO /* Receiver Overrun */
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#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
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+#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO Access Complete */
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+#define E1000_IMS_SRPD E1000_ICR_SRPD /* Small Receive Packet */
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+#define E1000_IMS_ACK E1000_ICR_ACK /* Receive ACK Frame Detected */
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+#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability Event */
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#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
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#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
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#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
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--- a/drivers/net/ethernet/intel/e1000e/netdev.c
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+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
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@@ -1910,16 +1910,12 @@ static irqreturn_t e1000_msix_other(int
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struct net_device *netdev = data;
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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- u32 icr;
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-
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- icr = er32(ICR);
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- ew32(ICR, E1000_ICR_OTHER);
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+ u32 icr = er32(ICR);
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if (icr & adapter->eiac_mask)
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ew32(ICS, (icr & adapter->eiac_mask));
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if (icr & E1000_ICR_LSC) {
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- ew32(ICR, E1000_ICR_LSC);
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hw->mac.get_link_status = true;
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/* guard against interrupt when we're going down */
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if (!test_bit(__E1000_DOWN, &adapter->state))
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@@ -1927,7 +1923,7 @@ static irqreturn_t e1000_msix_other(int
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}
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if (!test_bit(__E1000_DOWN, &adapter->state))
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- ew32(IMS, E1000_IMS_OTHER);
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+ ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
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return IRQ_HANDLED;
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}
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@@ -2254,7 +2250,8 @@ static void e1000_irq_enable(struct e100
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if (adapter->msix_entries) {
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ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
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- ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
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+ ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
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+ IMS_OTHER_MASK);
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} else if (hw->mac.type >= e1000_pch_lpt) {
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ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
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} else {
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Loading…
Reference in new issue