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@ -24,141 +24,141 @@ |
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#include <linux/debugfs.h> |
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#endif |
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#define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver" |
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#define RTL8366S_DRIVER_VER "0.2.2" |
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#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver" |
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#define RTL8366RB_DRIVER_VER "0.2.2" |
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#define RTL8366S_PHY_NO_MAX 4 |
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#define RTL8366S_PHY_PAGE_MAX 7 |
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#define RTL8366S_PHY_ADDR_MAX 31 |
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#define RTL8366RB_PHY_NO_MAX 4 |
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#define RTL8366RB_PHY_PAGE_MAX 7 |
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#define RTL8366RB_PHY_ADDR_MAX 31 |
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#define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000 |
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#define RTL8366_CHIP_CTRL_VLAN (1 << 13) |
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#define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14) |
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#define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000 |
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#define RTL8366RB_CHIP_CTRL_VLAN (1 << 13) |
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#define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14) |
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/* Switch Global Configuration register */ |
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#define RTL8366_SGCR 0x0000 |
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#define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0) |
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#define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4) |
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#define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3) |
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#define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0) |
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#define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1) |
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#define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2) |
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#define RTL8366_SGCR_MAX_LENGTH_9216 RTL8366_SGCR_MAX_LENGTH(0x3) |
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#define RTL8366RB_SGCR 0x0000 |
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#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0) |
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#define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4) |
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#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3) |
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#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0) |
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#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1) |
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#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2) |
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#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3) |
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/* Port Enable Control register */ |
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#define RTL8366_PECR 0x0001 |
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#define RTL8366RB_PECR 0x0001 |
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/* Switch Security Control registers */ |
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#define RTL8366_SSCR0 0x0002 |
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#define RTL8366_SSCR1 0x0003 |
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#define RTL8366_SSCR2 0x0004 |
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#define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0) |
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#define RTL8366RB_SSCR0 0x0002 |
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#define RTL8366RB_SSCR1 0x0003 |
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#define RTL8366RB_SSCR2 0x0004 |
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#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) |
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#define RTL8366_RESET_CTRL_REG 0x0100 |
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#define RTL8366_CHIP_CTRL_RESET_HW 1 |
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#define RTL8366_CHIP_CTRL_RESET_SW (1 << 1) |
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#define RTL8366RB_RESET_CTRL_REG 0x0100 |
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#define RTL8366RB_CHIP_CTRL_RESET_HW 1 |
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#define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1) |
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#define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A |
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#define RTL8366S_CHIP_VERSION_MASK 0xf |
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#define RTL8366S_CHIP_ID_REG 0x0509 |
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#define RTL8366S_CHIP_ID_8366 0x5937 |
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#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A |
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#define RTL8366RB_CHIP_VERSION_MASK 0xf |
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#define RTL8366RB_CHIP_ID_REG 0x0509 |
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#define RTL8366RB_CHIP_ID_8366 0x5937 |
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/* PHY registers control */ |
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#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000 |
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#define RTL8366S_PHY_ACCESS_DATA_REG 0x8002 |
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#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000 |
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#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002 |
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#define RTL8366S_PHY_CTRL_READ 1 |
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#define RTL8366S_PHY_CTRL_WRITE 0 |
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#define RTL8366RB_PHY_CTRL_READ 1 |
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#define RTL8366RB_PHY_CTRL_WRITE 0 |
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#define RTL8366S_PHY_REG_MASK 0x1f |
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#define RTL8366S_PHY_PAGE_OFFSET 5 |
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#define RTL8366S_PHY_PAGE_MASK (0xf << 5) |
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#define RTL8366S_PHY_NO_OFFSET 9 |
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#define RTL8366S_PHY_NO_MASK (0x1f << 9) |
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#define RTL8366RB_PHY_REG_MASK 0x1f |
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#define RTL8366RB_PHY_PAGE_OFFSET 5 |
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#define RTL8366RB_PHY_PAGE_MASK (0xf << 5) |
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#define RTL8366RB_PHY_NO_OFFSET 9 |
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#define RTL8366RB_PHY_NO_MASK (0x1f << 9) |
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/* LED control registers */ |
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#define RTL8366_LED_BLINKRATE_REG 0x0430 |
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#define RTL8366_LED_BLINKRATE_BIT 0 |
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#define RTL8366_LED_BLINKRATE_MASK 0x0007 |
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#define RTL8366RB_LED_BLINKRATE_REG 0x0430 |
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#define RTL8366RB_LED_BLINKRATE_BIT 0 |
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#define RTL8366RB_LED_BLINKRATE_MASK 0x0007 |
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#define RTL8366_LED_CTRL_REG 0x0431 |
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#define RTL8366_LED_0_1_CTRL_REG 0x0432 |
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#define RTL8366_LED_2_3_CTRL_REG 0x0433 |
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#define RTL8366RB_LED_CTRL_REG 0x0431 |
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#define RTL8366RB_LED_0_1_CTRL_REG 0x0432 |
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#define RTL8366RB_LED_2_3_CTRL_REG 0x0433 |
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#define RTL8366S_MIB_COUNT 33 |
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#define RTL8366S_GLOBAL_MIB_COUNT 1 |
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#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050 |
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#define RTL8366S_MIB_COUNTER_BASE 0x1000 |
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#define RTL8366S_MIB_CTRL_REG 0x13F0 |
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#define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC |
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#define RTL8366S_MIB_CTRL_BUSY_MASK BIT(0) |
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#define RTL8366S_MIB_CTRL_RESET_MASK BIT(1) |
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#define RTL8366S_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p)) |
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#define RTL8366S_MIB_CTRL_GLOBAL_RESET BIT(11) |
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#define RTL8366RB_MIB_COUNT 33 |
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#define RTL8366RB_GLOBAL_MIB_COUNT 1 |
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#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050 |
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#define RTL8366RB_MIB_COUNTER_BASE 0x1000 |
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#define RTL8366RB_MIB_CTRL_REG 0x13F0 |
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#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC |
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#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0) |
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#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1) |
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#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p)) |
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#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11) |
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#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063 |
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#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \ |
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(RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4) |
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#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf |
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#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) |
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#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063 |
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#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \ |
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(RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4) |
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#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf |
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#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) |
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#define RTL8366S_VLAN_TABLE_READ_BASE 0x018C |
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#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185 |
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#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C |
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#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185 |
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#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180 |
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#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01 |
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#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01 |
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#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180 |
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#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01 |
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#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01 |
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#define RTL8366S_VLAN_MEMCONF_BASE 0x0020 |
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#define RTL8366RB_VLAN_MEMCONF_BASE 0x0020 |
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#define RTL8366S_PORT_LINK_STATUS_BASE 0x0014 |
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#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003 |
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#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004 |
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#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010 |
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#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020 |
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#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040 |
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#define RTL8366S_PORT_STATUS_AN_MASK 0x0080 |
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#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014 |
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#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003 |
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#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004 |
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#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010 |
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#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020 |
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#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040 |
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#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080 |
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#define RTL8366_PORT_NUM_CPU 5 |
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#define RTL8366_NUM_PORTS 6 |
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#define RTL8366_NUM_VLANS 16 |
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#define RTL8366_NUM_LEDGROUPS 4 |
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#define RTL8366_NUM_VIDS 4096 |
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#define RTL8366S_PRIORITYMAX 7 |
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#define RTL8366S_FIDMAX 7 |
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#define RTL8366RB_PORT_NUM_CPU 5 |
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#define RTL8366RB_NUM_PORTS 6 |
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#define RTL8366RB_NUM_VLANS 16 |
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#define RTL8366RB_NUM_LEDGROUPS 4 |
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#define RTL8366RB_NUM_VIDS 4096 |
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#define RTL8366RB_PRIORITYMAX 7 |
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#define RTL8366RB_FIDMAX 7 |
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#define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */ |
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#define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */ |
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#define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */ |
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#define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */ |
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#define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */ |
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#define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */ |
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#define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */ |
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#define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */ |
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#define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */ |
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#define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */ |
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#define RTL8366_PORT_CPU (1 << 5) /* CPU port */ |
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#define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */ |
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#define RTL8366_PORT_ALL (RTL8366_PORT_1 | \ |
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RTL8366_PORT_2 | \
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RTL8366_PORT_3 | \
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RTL8366_PORT_4 | \
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RTL8366_PORT_5 | \
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RTL8366_PORT_CPU) |
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#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \ |
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RTL8366RB_PORT_2 | \
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RTL8366RB_PORT_3 | \
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RTL8366RB_PORT_4 | \
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RTL8366RB_PORT_5 | \
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RTL8366RB_PORT_CPU) |
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#define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \ |
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RTL8366_PORT_2 | \
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RTL8366_PORT_3 | \
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RTL8366_PORT_4 | \
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RTL8366_PORT_5) |
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#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \ |
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RTL8366RB_PORT_2 | \
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RTL8366RB_PORT_3 | \
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RTL8366RB_PORT_4 | \
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RTL8366RB_PORT_5) |
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#define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \ |
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RTL8366_PORT_2 | \
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RTL8366_PORT_3 | \
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RTL8366_PORT_4) |
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#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \ |
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RTL8366RB_PORT_2 | \
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RTL8366RB_PORT_3 | \
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RTL8366RB_PORT_4) |
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#define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU |
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#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU |
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struct rtl8366rb { |
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struct device *parent; |
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@ -201,7 +201,7 @@ struct mib_counter { |
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const char *name; |
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}; |
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static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = { |
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static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = { |
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{ 0, 4, "IfInOctets" }, |
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{ 4, 4, "EtherStatsOctets" }, |
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{ 8, 2, "EtherStatsUnderSizePkts" }, |
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@ -272,14 +272,14 @@ static int rtl8366rb_reset_chip(struct rtl8366_smi *smi) |
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int timeout = 10; |
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u32 data; |
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rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG, |
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RTL8366_CHIP_CTRL_RESET_HW); |
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rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG, |
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RTL8366RB_CHIP_CTRL_RESET_HW); |
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do { |
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msleep(1); |
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if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data)) |
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if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data)) |
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return -EIO; |
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if (!(data & RTL8366_CHIP_CTRL_RESET_HW)) |
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if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW)) |
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break; |
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} while (--timeout); |
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@ -296,20 +296,20 @@ static int rtl8366rb_hw_init(struct rtl8366_smi *smi) |
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int err; |
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/* set maximum packet length to 1536 bytes */ |
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REG_RMW(smi, RTL8366_SGCR, RTL8366_SGCR_MAX_LENGTH_MASK, |
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RTL8366_SGCR_MAX_LENGTH_1536); |
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REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK, |
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RTL8366RB_SGCR_MAX_LENGTH_1536); |
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/* enable all ports */ |
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REG_WR(smi, RTL8366_PECR, 0); |
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REG_WR(smi, RTL8366RB_PECR, 0); |
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/* disable learning for all ports */ |
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REG_WR(smi, RTL8366_SSCR0, RTL8366_PORT_ALL); |
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REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL); |
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/* disable auto ageing for all ports */ |
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REG_WR(smi, RTL8366_SSCR1, RTL8366_PORT_ALL); |
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REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL); |
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/* don't drop packets whose DA has not been learned */ |
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REG_RMW(smi, RTL8366_SSCR2, RTL8366_SSCR2_DROP_UNKNOWN_DA, 0); |
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REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0); |
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return 0; |
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} |
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@ -320,29 +320,29 @@ static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi, |
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u32 reg; |
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int ret; |
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if (phy_no > RTL8366S_PHY_NO_MAX) |
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if (phy_no > RTL8366RB_PHY_NO_MAX) |
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return -EINVAL; |
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if (page > RTL8366S_PHY_PAGE_MAX) |
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if (page > RTL8366RB_PHY_PAGE_MAX) |
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return -EINVAL; |
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if (addr > RTL8366S_PHY_ADDR_MAX) |
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if (addr > RTL8366RB_PHY_ADDR_MAX) |
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return -EINVAL; |
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ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
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RTL8366S_PHY_CTRL_READ); |
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ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG, |
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RTL8366RB_PHY_CTRL_READ); |
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if (ret) |
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return ret; |
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reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
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((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
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(addr & RTL8366S_PHY_REG_MASK); |
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reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) | |
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((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) | |
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(addr & RTL8366RB_PHY_REG_MASK); |
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ret = rtl8366_smi_write_reg(smi, reg, 0); |
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if (ret) |
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return ret; |
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ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data); |
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ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data); |
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if (ret) |
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return ret; |
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@ -355,23 +355,23 @@ static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi, |
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u32 reg; |
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int ret; |
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if (phy_no > RTL8366S_PHY_NO_MAX) |
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if (phy_no > RTL8366RB_PHY_NO_MAX) |
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return -EINVAL; |
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if (page > RTL8366S_PHY_PAGE_MAX) |
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if (page > RTL8366RB_PHY_PAGE_MAX) |
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return -EINVAL; |
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if (addr > RTL8366S_PHY_ADDR_MAX) |
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if (addr > RTL8366RB_PHY_ADDR_MAX) |
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return -EINVAL; |
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ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
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RTL8366S_PHY_CTRL_WRITE); |
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ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG, |
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RTL8366RB_PHY_CTRL_WRITE); |
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if (ret) |
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return ret; |
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reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
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((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
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(addr & RTL8366S_PHY_REG_MASK); |
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reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) | |
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((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) | |
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(addr & RTL8366RB_PHY_REG_MASK); |
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ret = rtl8366_smi_write_reg(smi, reg, data); |
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if (ret) |
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@ -388,11 +388,11 @@ static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter, |
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u32 addr, data; |
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u64 mibvalue; |
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if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT) |
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if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT) |
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return -EINVAL; |
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addr = RTL8366S_MIB_COUNTER_BASE + |
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RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) + |
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addr = RTL8366RB_MIB_COUNTER_BASE + |
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RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) + |
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rtl8366rb_mib_counters[counter].offset; |
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/*
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@ -405,14 +405,14 @@ static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter, |
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return err; |
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/* read MIB control register */ |
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err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data); |
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err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data); |
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if (err) |
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return err; |
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if (data & RTL8366S_MIB_CTRL_BUSY_MASK) |
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if (data & RTL8366RB_MIB_CTRL_BUSY_MASK) |
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return -EBUSY; |
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if (data & RTL8366S_MIB_CTRL_RESET_MASK) |
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if (data & RTL8366RB_MIB_CTRL_RESET_MASK) |
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return -EIO; |
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mibvalue = 0; |
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@ -439,31 +439,31 @@ static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, |
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memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); |
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vlan4k_priv.vid = vid; |
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if (vid >= RTL8366_NUM_VIDS) |
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if (vid >= RTL8366RB_NUM_VIDS) |
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return -EINVAL; |
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tableaddr = (u16 *)&vlan4k_priv; |
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/* write VID */ |
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data = *tableaddr; |
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err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data); |
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err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data); |
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if (err) |
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return err; |
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/* write table access control word */ |
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err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
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RTL8366S_TABLE_VLAN_READ_CTRL); |
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err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG, |
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RTL8366RB_TABLE_VLAN_READ_CTRL); |
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if (err) |
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return err; |
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err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data); |
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err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data); |
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if (err) |
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return err; |
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*tableaddr = data; |
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tableaddr++; |
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err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1, |
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err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1, |
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&data); |
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if (err) |
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return err; |
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@ -471,7 +471,7 @@ static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, |
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*tableaddr = data; |
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tableaddr++; |
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err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2, |
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err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2, |
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&data); |
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if (err) |
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return err; |
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@ -493,10 +493,10 @@ static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi, |
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u32 data; |
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u16 *tableaddr; |
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if (vlan4k->vid >= RTL8366_NUM_VIDS || |
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vlan4k->member > RTL8366_PORT_ALL || |
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vlan4k->untag > RTL8366_PORT_ALL || |
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vlan4k->fid > RTL8366S_FIDMAX) |
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if (vlan4k->vid >= RTL8366RB_NUM_VIDS || |
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vlan4k->member > RTL8366RB_PORT_ALL || |
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vlan4k->untag > RTL8366RB_PORT_ALL || |
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vlan4k->fid > RTL8366RB_FIDMAX) |
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return -EINVAL; |
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vlan4k_priv.vid = vlan4k->vid; |
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@ -508,7 +508,7 @@ static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi, |
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data = *tableaddr; |
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err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data); |
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err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data); |
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if (err) |
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return err; |
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@ -516,7 +516,7 @@ static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi, |
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data = *tableaddr; |
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err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, |
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err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1, |
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data); |
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if (err) |
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return err; |
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@ -525,14 +525,14 @@ static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi, |
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data = *tableaddr; |
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err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2, |
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err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2, |
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data); |
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if (err) |
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return err; |
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/* write table access control word */ |
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err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
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RTL8366S_TABLE_VLAN_WRITE_CTRL); |
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err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG, |
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RTL8366RB_TABLE_VLAN_WRITE_CTRL); |
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return err; |
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} |
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@ -548,12 +548,12 @@ static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index, |
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memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); |
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if (index >= RTL8366_NUM_VLANS) |
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if (index >= RTL8366RB_NUM_VLANS) |
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return -EINVAL; |
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tableaddr = (u16 *)&vlanmc_priv; |
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addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3); |
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addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3); |
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err = rtl8366_smi_read_reg(smi, addr, &data); |
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if (err) |
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return err; |
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@ -561,7 +561,7 @@ static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index, |
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*tableaddr = data; |
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tableaddr++; |
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addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3); |
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addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3); |
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err = rtl8366_smi_read_reg(smi, addr, &data); |
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if (err) |
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return err; |
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@ -569,7 +569,7 @@ static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index, |
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*tableaddr = data; |
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tableaddr++; |
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addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3); |
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addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3); |
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err = rtl8366_smi_read_reg(smi, addr, &data); |
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if (err) |
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return err; |
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@ -594,12 +594,12 @@ static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
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u32 data; |
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u16 *tableaddr; |
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if (index >= RTL8366_NUM_VLANS || |
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vlanmc->vid >= RTL8366_NUM_VIDS || |
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vlanmc->priority > RTL8366S_PRIORITYMAX || |
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vlanmc->member > RTL8366_PORT_ALL || |
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vlanmc->untag > RTL8366_PORT_ALL || |
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vlanmc->fid > RTL8366S_FIDMAX) |
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if (index >= RTL8366RB_NUM_VLANS || |
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vlanmc->vid >= RTL8366RB_NUM_VIDS || |
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vlanmc->priority > RTL8366RB_PRIORITYMAX || |
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vlanmc->member > RTL8366RB_PORT_ALL || |
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vlanmc->untag > RTL8366RB_PORT_ALL || |
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vlanmc->fid > RTL8366RB_FIDMAX) |
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return -EINVAL; |
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vlanmc_priv.vid = vlanmc->vid; |
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@ -610,7 +610,7 @@ static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
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vlanmc_priv.stag_idx = 0; |
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vlanmc_priv.fid = vlanmc->fid; |
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addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3); |
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addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3); |
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tableaddr = (u16 *)&vlanmc_priv; |
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data = *tableaddr; |
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@ -619,7 +619,7 @@ static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
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|
|
if (err) |
|
|
|
|
return err; |
|
|
|
|
|
|
|
|
|
addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3); |
|
|
|
|
addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3); |
|
|
|
|
|
|
|
|
|
tableaddr++; |
|
|
|
|
data = *tableaddr; |
|
|
|
@ -628,7 +628,7 @@ static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
|
|
|
|
|
|
addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3); |
|
|
|
|
addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3); |
|
|
|
|
|
|
|
|
|
tableaddr++; |
|
|
|
|
data = *tableaddr; |
|
|
|
@ -644,16 +644,16 @@ static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val) |
|
|
|
|
u32 data; |
|
|
|
|
int err; |
|
|
|
|
|
|
|
|
|
if (port >= RTL8366_NUM_PORTS) |
|
|
|
|
if (port >= RTL8366RB_NUM_PORTS) |
|
|
|
|
return -EINVAL; |
|
|
|
|
|
|
|
|
|
err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
|
|
|
|
err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port), |
|
|
|
|
&data); |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
|
|
|
|
|
|
*val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) & |
|
|
|
|
RTL8366S_PORT_VLAN_CTRL_MASK; |
|
|
|
|
*val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) & |
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_MASK; |
|
|
|
|
|
|
|
|
|
return 0; |
|
|
|
|
|
|
|
|
@ -661,14 +661,14 @@ static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val) |
|
|
|
|
|
|
|
|
|
static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index) |
|
|
|
|
{ |
|
|
|
|
if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS) |
|
|
|
|
if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS) |
|
|
|
|
return -EINVAL; |
|
|
|
|
|
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
|
|
|
|
RTL8366S_PORT_VLAN_CTRL_MASK << |
|
|
|
|
RTL8366S_PORT_VLAN_CTRL_SHIFT(port), |
|
|
|
|
(index & RTL8366S_PORT_VLAN_CTRL_MASK) << |
|
|
|
|
RTL8366S_PORT_VLAN_CTRL_SHIFT(port)); |
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port), |
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_MASK << |
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_SHIFT(port), |
|
|
|
|
(index & RTL8366RB_PORT_VLAN_CTRL_MASK) << |
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int rtl8366rb_set_vlan(struct rtl8366_smi *smi, int vid, u32 member, |
|
|
|
@ -691,7 +691,7 @@ static int rtl8366rb_set_vlan(struct rtl8366_smi *smi, int vid, u32 member, |
|
|
|
|
return err; |
|
|
|
|
|
|
|
|
|
/* Try to find an existing MC entry for this VID */ |
|
|
|
|
for (i = 0; i < RTL8366_NUM_VLANS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_VLANS; i++) { |
|
|
|
|
struct rtl8366_vlan_mc vlanmc; |
|
|
|
|
|
|
|
|
|
err = rtl8366rb_get_vlan_mc(smi, i, &vlanmc); |
|
|
|
@ -737,7 +737,7 @@ static int rtl8366rb_mc_is_used(struct rtl8366_smi *smi, int mc_index, |
|
|
|
|
int i; |
|
|
|
|
|
|
|
|
|
*used = 0; |
|
|
|
|
for (i = 0; i < RTL8366_NUM_PORTS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { |
|
|
|
|
int index = 0; |
|
|
|
|
|
|
|
|
|
err = rtl8366rb_get_mc_index(smi, i, &index); |
|
|
|
@ -762,7 +762,7 @@ static int rtl8366rb_set_pvid(struct rtl8366_smi *smi, unsigned port, |
|
|
|
|
int i; |
|
|
|
|
|
|
|
|
|
/* Try to find an existing MC entry for this VID */ |
|
|
|
|
for (i = 0; i < RTL8366_NUM_VLANS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_VLANS; i++) { |
|
|
|
|
err = rtl8366rb_get_vlan_mc(smi, i, &vlanmc); |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
@ -778,7 +778,7 @@ static int rtl8366rb_set_pvid(struct rtl8366_smi *smi, unsigned port, |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* We have no MC entry for this VID, try to find an empty one */ |
|
|
|
|
for (i = 0; i < RTL8366_NUM_VLANS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_VLANS; i++) { |
|
|
|
|
err = rtl8366rb_get_vlan_mc(smi, i, &vlanmc); |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
@ -803,7 +803,7 @@ static int rtl8366rb_set_pvid(struct rtl8366_smi *smi, unsigned port, |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* MC table is full, try to find an unused entry and replace it */ |
|
|
|
|
for (i = 0; i < RTL8366_NUM_VLANS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_VLANS; i++) { |
|
|
|
|
int used; |
|
|
|
|
|
|
|
|
|
err = rtl8366rb_mc_is_used(smi, i, &used); |
|
|
|
@ -837,16 +837,16 @@ static int rtl8366rb_set_pvid(struct rtl8366_smi *smi, unsigned port, |
|
|
|
|
|
|
|
|
|
static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable) |
|
|
|
|
{ |
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, |
|
|
|
|
RTL8366_CHIP_CTRL_VLAN, |
|
|
|
|
(enable) ? RTL8366_CHIP_CTRL_VLAN : 0); |
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, |
|
|
|
|
RTL8366RB_CHIP_CTRL_VLAN, |
|
|
|
|
(enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable) |
|
|
|
|
{ |
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, |
|
|
|
|
RTL8366_CHIP_CTRL_VLAN_4KTB, |
|
|
|
|
(enable) ? RTL8366_CHIP_CTRL_VLAN_4KTB : 0); |
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, |
|
|
|
|
RTL8366RB_CHIP_CTRL_VLAN_4KTB, |
|
|
|
|
(enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi) |
|
|
|
@ -861,19 +861,19 @@ static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi) |
|
|
|
|
vlanmc.member = 0; |
|
|
|
|
vlanmc.untag = 0; |
|
|
|
|
vlanmc.fid = 0; |
|
|
|
|
for (i = 0; i < RTL8366_NUM_VLANS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_VLANS; i++) { |
|
|
|
|
err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc); |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
for (i = 0; i < RTL8366_NUM_PORTS; i++) { |
|
|
|
|
if (i == RTL8366_PORT_CPU) |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { |
|
|
|
|
if (i == RTL8366RB_PORT_CPU) |
|
|
|
|
continue; |
|
|
|
|
|
|
|
|
|
err = rtl8366rb_set_vlan(smi, (i + 1), |
|
|
|
|
(1 << i) | RTL8366_PORT_CPU, |
|
|
|
|
(1 << i) | RTL8366_PORT_CPU, |
|
|
|
|
(1 << i) | RTL8366RB_PORT_CPU, |
|
|
|
|
(1 << i) | RTL8366RB_PORT_CPU, |
|
|
|
|
0); |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
@ -911,7 +911,7 @@ static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file, |
|
|
|
|
for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) { |
|
|
|
|
len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ", |
|
|
|
|
rtl8366rb_mib_counters[i].name); |
|
|
|
|
for (j = 0; j < RTL8366_NUM_PORTS; ++j) { |
|
|
|
|
for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) { |
|
|
|
|
unsigned long long counter = 0; |
|
|
|
|
|
|
|
|
|
if (!rtl8366_get_mib_counter(smi, i, j, &counter)) |
|
|
|
@ -942,7 +942,7 @@ static ssize_t rtl8366rb_read_debugfs_vlan_mc(struct file *file, |
|
|
|
|
"%2s %6s %4s %6s %6s %3s\n", |
|
|
|
|
"id", "vid","prio", "member", "untag", "fid"); |
|
|
|
|
|
|
|
|
|
for (i = 0; i < RTL8366_NUM_VLANS; ++i) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_VLANS; ++i) { |
|
|
|
|
struct rtl8366_vlan_mc vlanmc; |
|
|
|
|
|
|
|
|
|
rtl8366rb_get_vlan_mc(smi, i, &vlanmc); |
|
|
|
@ -1104,8 +1104,8 @@ static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev, |
|
|
|
|
int err = 0; |
|
|
|
|
|
|
|
|
|
if (val->value.i == 1) |
|
|
|
|
err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, |
|
|
|
|
RTL8366S_MIB_CTRL_GLOBAL_RESET); |
|
|
|
|
err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0, |
|
|
|
|
RTL8366RB_MIB_CTRL_GLOBAL_RESET); |
|
|
|
|
|
|
|
|
|
return err; |
|
|
|
|
} |
|
|
|
@ -1118,16 +1118,16 @@ static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev, |
|
|
|
|
u32 data; |
|
|
|
|
|
|
|
|
|
if (attr->ofs == 1) { |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data); |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data); |
|
|
|
|
|
|
|
|
|
if (data & RTL8366_CHIP_CTRL_VLAN) |
|
|
|
|
if (data & RTL8366RB_CHIP_CTRL_VLAN) |
|
|
|
|
val->value.i = 1; |
|
|
|
|
else |
|
|
|
|
val->value.i = 0; |
|
|
|
|
} else if (attr->ofs == 2) { |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data); |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data); |
|
|
|
|
|
|
|
|
|
if (data & RTL8366_CHIP_CTRL_VLAN_4KTB) |
|
|
|
|
if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB) |
|
|
|
|
val->value.i = 1; |
|
|
|
|
else |
|
|
|
|
val->value.i = 0; |
|
|
|
@ -1143,9 +1143,9 @@ static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev, |
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
|
|
|
u32 data; |
|
|
|
|
|
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data); |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data); |
|
|
|
|
|
|
|
|
|
val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK)); |
|
|
|
|
val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK)); |
|
|
|
|
|
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
@ -1159,8 +1159,8 @@ static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev, |
|
|
|
|
if (val->value.i >= 6) |
|
|
|
|
return -EINVAL; |
|
|
|
|
|
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, |
|
|
|
|
RTL8366_LED_BLINKRATE_MASK, |
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, |
|
|
|
|
RTL8366RB_LED_BLINKRATE_MASK, |
|
|
|
|
val->value.i); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -1198,29 +1198,29 @@ static int rtl8366rb_sw_get_port_link(struct switch_dev *dev, |
|
|
|
|
struct rtl8366_smi *smi = &rtl->smi; |
|
|
|
|
u32 len = 0, data = 0; |
|
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366_NUM_PORTS) |
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS) |
|
|
|
|
return -EINVAL; |
|
|
|
|
|
|
|
|
|
memset(rtl->buf, '\0', sizeof(rtl->buf)); |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + |
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + |
|
|
|
|
(val->port_vlan / 2), &data); |
|
|
|
|
|
|
|
|
|
if (val->port_vlan % 2) |
|
|
|
|
data = data >> 8; |
|
|
|
|
|
|
|
|
|
if (data & RTL8366S_PORT_STATUS_LINK_MASK) { |
|
|
|
|
if (data & RTL8366RB_PORT_STATUS_LINK_MASK) { |
|
|
|
|
len = snprintf(rtl->buf, sizeof(rtl->buf), |
|
|
|
|
"port:%d link:up speed:%s %s-duplex %s%s%s", |
|
|
|
|
val->port_vlan, |
|
|
|
|
rtl8366rb_speed_str(data & |
|
|
|
|
RTL8366S_PORT_STATUS_SPEED_MASK), |
|
|
|
|
(data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ? |
|
|
|
|
RTL8366RB_PORT_STATUS_SPEED_MASK), |
|
|
|
|
(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ? |
|
|
|
|
"full" : "half", |
|
|
|
|
(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ? |
|
|
|
|
(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ? |
|
|
|
|
"tx-pause ": "", |
|
|
|
|
(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ? |
|
|
|
|
(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ? |
|
|
|
|
"rx-pause " : "", |
|
|
|
|
(data & RTL8366S_PORT_STATUS_AN_MASK) ? |
|
|
|
|
(data & RTL8366RB_PORT_STATUS_AN_MASK) ? |
|
|
|
|
"nway ": ""); |
|
|
|
|
} else { |
|
|
|
|
len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down", |
|
|
|
@ -1245,7 +1245,7 @@ static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev, |
|
|
|
|
char *buf = rtl->buf; |
|
|
|
|
int err; |
|
|
|
|
|
|
|
|
|
if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS) |
|
|
|
|
if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS) |
|
|
|
|
return -EINVAL; |
|
|
|
|
|
|
|
|
|
memset(buf, '\0', sizeof(rtl->buf)); |
|
|
|
@ -1257,7 +1257,7 @@ static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev, |
|
|
|
|
len += snprintf(buf + len, sizeof(rtl->buf) - len, |
|
|
|
|
"VLAN %d: Ports: '", vlan4k.vid); |
|
|
|
|
|
|
|
|
|
for (i = 0; i < RTL8366_NUM_PORTS; i++) { |
|
|
|
|
for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { |
|
|
|
|
if (!(vlan4k.member & (1 << i))) |
|
|
|
|
continue; |
|
|
|
|
|
|
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@ -1284,20 +1284,20 @@ static int rtl8366rb_sw_set_port_led(struct switch_dev *dev, |
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u32 mask; |
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u32 reg; |
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if (val->port_vlan >= RTL8366_NUM_PORTS) |
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if (val->port_vlan >= RTL8366RB_NUM_PORTS) |
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return -EINVAL; |
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if (val->port_vlan == RTL8366_PORT_NUM_CPU) { |
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reg = RTL8366_LED_BLINKRATE_REG; |
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if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) { |
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reg = RTL8366RB_LED_BLINKRATE_REG; |
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mask = 0xF << 4; |
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data = val->value.i << 4; |
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} else { |
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reg = RTL8366_LED_CTRL_REG; |
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reg = RTL8366RB_LED_CTRL_REG; |
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mask = 0xF << (val->port_vlan * 4), |
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data = val->value.i << (val->port_vlan * 4); |
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} |
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return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data); |
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return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data); |
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} |
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static int rtl8366rb_sw_get_port_led(struct switch_dev *dev, |
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@ -1307,10 +1307,10 @@ static int rtl8366rb_sw_get_port_led(struct switch_dev *dev, |
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struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
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u32 data = 0; |
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if (val->port_vlan >= RTL8366_NUM_LEDGROUPS) |
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if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS) |
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return -EINVAL; |
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rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data); |
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rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data); |
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val->value.i = (data >> (val->port_vlan * 4)) & 0x000F; |
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return 0; |
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@ -1322,11 +1322,11 @@ static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev, |
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{ |
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struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
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if (val->port_vlan >= RTL8366_NUM_PORTS) |
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if (val->port_vlan >= RTL8366RB_NUM_PORTS) |
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return -EINVAL; |
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return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, |
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RTL8366S_MIB_CTRL_PORT_RESET(val->port_vlan)); |
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return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0, |
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RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan)); |
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} |
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static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev, |
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@ -1339,7 +1339,7 @@ static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev, |
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unsigned long long counter = 0; |
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char *buf = rtl->buf; |
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if (val->port_vlan >= RTL8366_NUM_PORTS) |
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if (val->port_vlan >= RTL8366RB_NUM_PORTS) |
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return -EINVAL; |
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len += snprintf(buf + len, sizeof(rtl->buf) - len, |
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@ -1370,14 +1370,14 @@ static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev, |
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struct rtl8366_vlan_4k vlan4k; |
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int i; |
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if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS) |
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if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS) |
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return -EINVAL; |
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rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k); |
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port = &val->value.ports[0]; |
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val->len = 0; |
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for (i = 0; i < RTL8366_NUM_PORTS; i++) { |
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for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { |
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if (!(vlan4k.member & BIT(i))) |
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continue; |
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@ -1399,7 +1399,7 @@ static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev, |
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u32 untag = 0; |
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int i; |
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if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS) |
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if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS) |
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return -EINVAL; |
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port = &val->value.ports[0]; |
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@ -1522,9 +1522,9 @@ static struct switch_attr rtl8366rb_vlan[] = { |
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/* template */ |
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static struct switch_dev rtl8366_switch_dev = { |
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.name = "RTL8366S", |
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.cpu_port = RTL8366_PORT_NUM_CPU, |
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.ports = RTL8366_NUM_PORTS, |
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.vlans = RTL8366_NUM_VLANS, |
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.cpu_port = RTL8366RB_PORT_NUM_CPU, |
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.ports = RTL8366RB_NUM_PORTS, |
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.vlans = RTL8366RB_NUM_VLANS, |
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.attr_global = { |
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.attr = rtl8366rb_globals, |
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.n_attr = ARRAY_SIZE(rtl8366rb_globals), |
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@ -1619,21 +1619,21 @@ static int rtl8366rb_detect(struct rtl8366_smi *smi) |
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u32 chip_ver = 0; |
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int ret; |
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ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id); |
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ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id); |
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if (ret) { |
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dev_err(smi->parent, "unable to read chip id\n"); |
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return ret; |
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} |
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switch (chip_id) { |
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case RTL8366S_CHIP_ID_8366: |
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case RTL8366RB_CHIP_ID_8366: |
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break; |
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default: |
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dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id); |
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return -ENODEV; |
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} |
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ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG, |
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ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG, |
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&chip_ver); |
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if (ret) { |
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dev_err(smi->parent, "unable to read chip version\n"); |
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@ -1641,7 +1641,7 @@ static int rtl8366rb_detect(struct rtl8366_smi *smi) |
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} |
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dev_info(smi->parent, "RTL%04x ver. %u chip found\n", |
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chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK); |
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chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK); |
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return 0; |
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} |
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@ -1661,8 +1661,8 @@ static int __init rtl8366rb_probe(struct platform_device *pdev) |
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int err; |
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if (!rtl8366_smi_version_printed++) |
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printk(KERN_NOTICE RTL8366S_DRIVER_DESC |
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" version " RTL8366S_DRIVER_VER"\n"); |
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printk(KERN_NOTICE RTL8366RB_DRIVER_DESC |
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" version " RTL8366RB_DRIVER_VER"\n"); |
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pdata = pdev->dev.platform_data; |
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if (!pdata) { |
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@ -1787,8 +1787,8 @@ static void __exit rtl8366rb_module_exit(void) |
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} |
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module_exit(rtl8366rb_module_exit); |
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MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC); |
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MODULE_VERSION(RTL8366S_DRIVER_VER); |
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MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC); |
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MODULE_VERSION(RTL8366RB_DRIVER_VER); |
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
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MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>"); |
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MODULE_LICENSE("GPL v2"); |
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