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@ -129,10 +129,10 @@ enum bcm63xx_regs_set { |
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#define BCM_6338_UART0_BASE (0xfffe0300) |
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#define BCM_6338_GPIO_BASE (0xfffe0400) |
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#define BCM_6338_SPI_BASE (0xfffe0c00) |
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#define BCM_6338_UDC0_BASE (0xdeadbeef) |
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#define BCM_6338_UDC0_BASE (0xfffe3000) |
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#define BCM_6338_USBDMA_BASE (0xfffe2400) |
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#define BCM_6338_OHCI0_BASE (0xdeadbeef) |
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#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) |
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#define BCM_6338_OHCI_PRIV_BASE (0xdeadbeef) |
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) |
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#define BCM_6338_MPI_BASE (0xfffe3160) |
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef) |
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@ -159,14 +159,14 @@ enum bcm63xx_regs_set { |
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#define BCM_6345_UART0_BASE (0xfffe0300) |
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#define BCM_6345_GPIO_BASE (0xfffe0400) |
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#define BCM_6345_SPI_BASE (0xdeadbeef) |
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#define BCM_6345_UDC0_BASE (0xdeadbeef) |
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#define BCM_6345_USBDMA_BASE (0xfffe2800) |
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#define BCM_6345_UDC0_BASE (0xfffe2100) |
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#define BCM_6345_USBDMA_BASE (0xfffe2b00) |
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#define BCM_6345_ENET0_BASE (0xfffe1800) |
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#define BCM_6345_ENETDMA_BASE (0xfffe2800) |
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#define BCM_6345_PCMCIA_BASE (0xfffe2028) |
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#define BCM_6345_MPI_BASE (0xdeadbeef) |
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#define BCM_6345_OHCI0_BASE (0xfffe2100) |
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) |
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#define BCM_6345_OHCI0_BASE (0xdeadbeef) |
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#define BCM_6345_OHCI_PRIV_BASE (0xdeadbeef) |
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) |
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#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) |
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#define BCM_6345_DSL_BASE (0xdeadbeef) |
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@ -598,7 +598,7 @@ enum bcm63xx_irq { |
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#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
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#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) |
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#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) |
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#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) |
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#define BCM_6345_UDC0_IRQ (IRQ_INTERNAL_BASE + 5) |
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#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
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#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
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#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) |
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