ramips: set clk_is_20mhz for rt2x00 on RT3352/RT5350

Signed-off-by: Daniel Golle <dgolle@allnet.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34270

target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h

@@ -111,6 +111,8 @@
 #define RT5350_SYSCFG0_DRAM_SIZE_32M	3
 #define RT5350_SYSCFG0_DRAM_SIZE_64M	4
 
+#define RT3352_SYSCFG0_XTAL_SEL		BIT(20)
+
 #define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
 
 #define RT3352_CLKCFG1_UPHY0_CLK_EN	BIT(18)

target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c

@@ -215,7 +215,15 @@ static struct platform_device rt305x_wifi_device = {
 
 void __init rt305x_register_wifi(void)
 {
+	u32 t;
 	rt305x_wifi_data.eeprom_file_name = "RT305X.eeprom";
+
+	if (soc_is_rt3352() || soc_is_rt5350()) {
+		t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
+		t &= RT3352_SYSCFG0_XTAL_SEL;
+		if (!t)
+			rt305x_wifi_data.clk_is_20mhz = 1;
+	}
 	platform_device_register(&rt305x_wifi_device);
 }