OpenWrt can be flashed with following uboot commands: tftpboot 0x80500000 openwrt-ar71xx-generic-wpj342-16M-squashfs-sysupgrade.bin erase 0x9f030000 +$filesize cp.b $fileaddr 0x9f030000 $filesize Signed-off-by: Christian Mehlis <christian@m3hlis.de> SVN-Revision: 49157
John Crispin
8 years ago
parent
2cba297ea0
commit
d9799dea89
@ -0,0 +1,178 @@ |
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/*
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* Compex WPJ342 board support |
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* |
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* Copyright (c) 2011 Qualcomm Atheros |
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* Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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* |
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*/ |
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#include <linux/irq.h> |
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#include <linux/pci.h> |
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#include <linux/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/ath9k_platform.h> |
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#include <linux/ar8216_platform.h> |
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#include <linux/export.h> |
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#include <asm/mach-ath79/ar71xx_regs.h> |
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#include "pci.h" |
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#include "common.h" |
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#include "dev-ap9x-pci.h" |
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#include "dev-eth.h" |
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#include "dev-gpio-buttons.h" |
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#include "dev-leds-gpio.h" |
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#include "dev-m25p80.h" |
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#include "dev-nfc.h" |
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#include "dev-spi.h" |
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#include "dev-usb.h" |
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#include "dev-wmac.h" |
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#include "machtypes.h" |
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#define WPJ342_GPIO_LED_STATUS 11 |
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#define WPJ342_GPIO_LED_SIG1 14 |
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#define WPJ342_GPIO_LED_SIG2 13 |
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#define WPJ342_GPIO_LED_SIG3 12 |
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#define WPJ342_GPIO_LED_SIG4 11 |
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#define WPJ342_GPIO_BUZZER 15 |
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#define WPJ342_GPIO_BTN_RESET 17 |
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#define WPJ342_KEYS_POLL_INTERVAL 20 /* msecs */ |
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#define WPJ342_KEYS_DEBOUNCE_INTERVAL (3 * WPJ342_KEYS_POLL_INTERVAL) |
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#define WPJ342_MAC0_OFFSET 0x10 |
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#define WPJ342_MAC1_OFFSET 0x18 |
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#define WPJ342_WMAC_CALDATA_OFFSET 0x1000 |
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#define WPJ342_PCIE_CALDATA_OFFSET 0x5000 |
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#define WPJ342_ART_SIZE 0x8000 |
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static struct gpio_led wpj342_leds_gpio[] __initdata = { |
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{ |
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.name = "wpj342:red:sig1", |
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.gpio = WPJ342_GPIO_LED_SIG1, |
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.active_low = 1, |
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}, |
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{ |
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.name = "wpj342:yellow:sig2", |
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.gpio = WPJ342_GPIO_LED_SIG2, |
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.active_low = 1, |
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}, |
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{ |
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.name = "wpj342:green:sig3", |
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.gpio = WPJ342_GPIO_LED_SIG3, |
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.active_low = 1, |
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}, |
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{ |
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.name = "wpj342:green:sig4", |
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.gpio = WPJ342_GPIO_LED_SIG4, |
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.active_low = 1, |
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}, |
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{ |
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.name = "wpj342:buzzer", |
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.gpio = WPJ342_GPIO_BUZZER, |
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.active_low = 0, |
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} |
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}; |
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static struct gpio_keys_button wpj342_gpio_keys[] __initdata = { |
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{ |
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.desc = "reset", |
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.type = EV_KEY, |
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.code = KEY_RESTART, |
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.debounce_interval = WPJ342_KEYS_DEBOUNCE_INTERVAL, |
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.gpio = WPJ342_GPIO_BTN_RESET, |
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.active_low = 1, |
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}, |
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}; |
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static struct ar8327_pad_cfg wpj342_ar8327_pad0_cfg = { |
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.mode = AR8327_PAD_MAC_RGMII, |
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.txclk_delay_en = true, |
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.rxclk_delay_en = true, |
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.txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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}; |
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static struct ar8327_led_cfg wpj342_ar8327_led_cfg = { |
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.led_ctrl0 = 0x00000000, |
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.led_ctrl1 = 0xc737c737, |
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.led_ctrl2 = 0x00000000, |
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.led_ctrl3 = 0x00c30c00, |
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.open_drain = true, |
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}; |
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static struct ar8327_platform_data wpj342_ar8327_data = { |
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.pad0_cfg = &wpj342_ar8327_pad0_cfg, |
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.port0_cfg = { |
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.force_link = 1, |
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.speed = AR8327_PORT_SPEED_1000, |
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.duplex = 1, |
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.txpause = 1, |
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.rxpause = 1, |
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}, |
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.led_cfg = &wpj342_ar8327_led_cfg, |
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}; |
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static struct mdio_board_info wpj342_mdio0_info[] = { |
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{ |
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.bus_id = "ag71xx-mdio.0", |
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.phy_addr = 0, |
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.platform_data = &wpj342_ar8327_data, |
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}, |
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}; |
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static void __init wpj342_setup(void) |
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{ |
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000); |
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ath79_register_m25p80(NULL); |
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ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio), |
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wpj342_leds_gpio); |
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ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL, |
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ARRAY_SIZE(wpj342_gpio_keys), |
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wpj342_gpio_keys); |
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ath79_register_usb(); |
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ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL); |
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ath79_register_pci(); |
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mdiobus_register_board_info(wpj342_mdio0_info, |
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ARRAY_SIZE(wpj342_mdio0_info)); |
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ath79_register_mdio(1, 0x0); |
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ath79_register_mdio(0, 0x0); |
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ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0); |
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ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0); |
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0); |
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/* GMAC0 is connected to an AR8236 switch */ |
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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ath79_eth0_data.phy_mask = BIT(0); |
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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ath79_eth0_pll_data.pll_1000 = 0x06000000; |
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ath79_register_eth(0); |
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} |
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MIPS_MACHINE(ATH79_MACH_WPJ342, "WPJ342", "Compex WPJ342", wpj342_setup); |
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