make openwrt boot on ar9130 (currently no ethernet yet)

SVN-Revision: 12463

target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

@@ -30,6 +30,7 @@
 
 #define AR71XX_SYS_TYPE_LEN	64
 #define AR71XX_BASE_FREQ	40000000
+#define AR91XX_BASE_FREQ	5000000
 
 #define AR71XX_MEM_SIZE_MIN	0x0200000
 #define AR71XX_MEM_SIZE_MAX	0x8000000
@@ -128,6 +129,9 @@ static void __init ar71xx_detect_sys_type(void)
 	case REV_ID_CHIP_AR7161:
 		chip = "7161";
 		break;
+	case REV_ID_CHIP_AR9130:
+		chip = "9130";
+		break;
 	default:
 		chip = "71xx";
 	}
@@ -136,24 +140,49 @@ static void __init ar71xx_detect_sys_type(void)
 		chip, rev, id);
 }
 
+static void __init ar91xx_detect_sys_frequency(void)
+{
+	u32 pll;
+	u32 freq;
+	u32 div;
+
+	pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
+
+	div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
+	freq = div * AR91XX_BASE_FREQ;
+
+	ar71xx_cpu_freq = freq;
+
+	div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
+	ar71xx_ddr_freq = freq / div;
+
+	div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
+	ar71xx_ahb_freq = ar71xx_cpu_freq / div;
+}
+
 static void __init ar71xx_detect_sys_frequency(void)
 {
 	u32 pll;
 	u32 freq;
 	u32 div;
 
+	if ((ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK) >=
+			REV_ID_CHIP_AR9130) {
+		return ar91xx_detect_sys_frequency();
+	}
+
 	pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
 
-	div = ((pll >> PLL_DIV_SHIFT) & PLL_DIV_MASK) + 1;
+	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 	freq = div * AR71XX_BASE_FREQ;
 
-	div = ((pll >> CPU_DIV_SHIFT) & CPU_DIV_MASK) + 1;
+	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 	ar71xx_cpu_freq = freq / div;
 
-	div = ((pll >> DDR_DIV_SHIFT) & DDR_DIV_MASK) + 1;
+	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 	ar71xx_ddr_freq = freq / div;
 
-	div = (((pll >> AHB_DIV_SHIFT) & AHB_DIV_MASK) + 1) * 2;
+	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 	ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 }
 

target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h

@@ -103,14 +103,21 @@ extern u32 ar71xx_ddr_freq;
 #define PLL_REG_ETH_EXT_CLK	0x18
 #define PLL_REG_PCI_CLK		0x1c
 
-#define PLL_DIV_SHIFT		3
-#define PLL_DIV_MASK		0x1f
-#define CPU_DIV_SHIFT		16
-#define CPU_DIV_MASK		0x3
-#define DDR_DIV_SHIFT		18
-#define DDR_DIV_MASK		0x3
-#define AHB_DIV_SHIFT		20
-#define AHB_DIV_MASK		0x7
+#define AR71XX_PLL_DIV_SHIFT		3
+#define AR71XX_PLL_DIV_MASK		0x1f
+#define AR71XX_CPU_DIV_SHIFT		16
+#define AR71XX_CPU_DIV_MASK		0x3
+#define AR71XX_DDR_DIV_SHIFT		18
+#define AR71XX_DDR_DIV_MASK		0x3
+#define AR71XX_AHB_DIV_SHIFT		20
+#define AR71XX_AHB_DIV_MASK		0x7
+
+#define AR91XX_PLL_DIV_SHIFT		0
+#define AR91XX_PLL_DIV_MASK		0x3ff
+#define AR91XX_DDR_DIV_SHIFT		22
+#define AR91XX_DDR_DIV_MASK		0x3
+#define AR91XX_AHB_DIV_SHIFT		19
+#define AR91XX_AHB_DIV_MASK		0x1
 
 extern void __iomem *ar71xx_pll_base;
 
@@ -306,6 +313,7 @@ extern void ar71xx_ddr_flush(u32 reg);
 #define REV_ID_CHIP_AR7130	0xa0
 #define REV_ID_CHIP_AR7141	0xa1
 #define REV_ID_CHIP_AR7161	0xa2
+#define REV_ID_CHIP_AR9130	0xb0
 
 #define REV_ID_REVISION_MASK	0x3
 #define REV_ID_REVISION_SHIFT	2