In order to prevent the impact of the merger of the company and the potential rebase of the SDK repositories, migrate the u-boot source to github. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>master
Yutang Jiang
8 years ago
committed by
John Crispin
parent
b0ac825884
commit
d5fc7430ca
@ -1,214 +0,0 @@ |
||||
From e03f571b1e9564ca422134b2013d80c8373c9db2 Mon Sep 17 00:00:00 2001
|
||||
From: Alison Wang <b18965@freescale.com>
|
||||
Date: Fri, 13 May 2016 10:19:24 +0800
|
||||
Subject: [PATCH 01/93] armv8: Support loading 32-bit OS in AArch32 execution
|
||||
state
|
||||
|
||||
To support loading a 32-bit OS, the execution state will change from
|
||||
AArch64 to AArch32 when jumping to kernel.
|
||||
|
||||
The architecture information will be got through checking FIT
|
||||
image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
|
||||
|
||||
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
|
||||
Signed-off-by: Alison Wang <alison.wang@nxp.com>
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/transition.S | 100 +++++++++++++++++++++++++++++++++++++++
|
||||
arch/arm/include/asm/system.h | 2 +
|
||||
arch/arm/lib/bootm.c | 20 +++++++-
|
||||
common/image-fit.c | 12 ++++-
|
||||
4 files changed, 131 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
|
||||
index 253a39b..9d7a17a 100644
|
||||
--- a/arch/arm/cpu/armv8/transition.S
|
||||
+++ b/arch/arm/cpu/armv8/transition.S
|
||||
@@ -21,3 +21,103 @@ ENTRY(armv8_switch_to_el1)
|
||||
0: ret
|
||||
1: armv8_switch_to_el1_m x0, x1
|
||||
ENDPROC(armv8_switch_to_el1)
|
||||
+
|
||||
+/*
|
||||
+ * x0: kernel entry point
|
||||
+ * x1: machine nr
|
||||
+ * x2: fdt address
|
||||
+ */
|
||||
+ENTRY(armv8_switch_to_el2_aarch32)
|
||||
+ switch_el x3, 1f, 0f, 0f
|
||||
+0: ret
|
||||
+1:
|
||||
+ mov x7, x0
|
||||
+ mov x8, x1
|
||||
+ mov x9, x2
|
||||
+
|
||||
+ /* 32bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
|
||||
+ mov x1, 0x1b1
|
||||
+ msr scr_el3, x1
|
||||
+ msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
|
||||
+ mov x1, 0x33ff
|
||||
+ msr cptr_el2, x1 /* Disable coprocessor traps to EL2 */
|
||||
+
|
||||
+ /* Initialize Generic Timers */
|
||||
+ msr cntvoff_el2, xzr
|
||||
+
|
||||
+ mov x1, #0x0830
|
||||
+ movk x1, #0x30c5, lsl #16
|
||||
+ msr sctlr_el2, x1
|
||||
+
|
||||
+ /* Return to AArch32 Hypervisor mode */
|
||||
+ mov x1, sp
|
||||
+ msr sp_el2, x1
|
||||
+ mrs x1, vbar_el3
|
||||
+ msr vbar_el2, x1 /* Migrate VBAR */
|
||||
+ mov x1, #0x1da
|
||||
+ msr spsr_el3, x1
|
||||
+ msr elr_el3, x7
|
||||
+
|
||||
+ mov x0, #0
|
||||
+ mov x1, x8
|
||||
+ mov x2, x9
|
||||
+
|
||||
+ eret
|
||||
+ENDPROC(armv8_switch_to_el2_aarch32)
|
||||
+
|
||||
+/*
|
||||
+ * x0: kernel entry point
|
||||
+ * x1: machine nr
|
||||
+ * x2: fdt address
|
||||
+ */
|
||||
+ENTRY(armv8_switch_to_el1_aarch32)
|
||||
+ switch_el x3, 0f, 1f, 0f
|
||||
+0: ret
|
||||
+1:
|
||||
+ mov x7, x0
|
||||
+ mov x8, x1
|
||||
+ mov x9, x2
|
||||
+
|
||||
+ /* Initialize Generic Timers */
|
||||
+ mrs x0, cnthctl_el2
|
||||
+ orr x0, x0, #0x3 /* Enable EL1 access to timers */
|
||||
+ msr cnthctl_el2, x0
|
||||
+ msr cntvoff_el2, xzr
|
||||
+
|
||||
+ /* Initialize MPID/MPIDR registers */
|
||||
+ mrs x0, midr_el1
|
||||
+ mrs x1, mpidr_el1
|
||||
+ msr vpidr_el2, x0
|
||||
+ msr vmpidr_el2, x1
|
||||
+
|
||||
+ /* Disable coprocessor traps */
|
||||
+ mov x0, #0x33ff
|
||||
+ msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
|
||||
+ msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
|
||||
+ mov x0, #3 << 20
|
||||
+ msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
|
||||
+
|
||||
+ /* Initialize HCR_EL2 */
|
||||
+ mov x0, #(0 << 31) /* 32bit EL1 */
|
||||
+ orr x0, x0, #(1 << 29) /* Disable HVC */
|
||||
+ msr hcr_el2, x0
|
||||
+
|
||||
+ mov x0, #0x0800
|
||||
+ movk x0, #0x30d0, lsl #16
|
||||
+ msr sctlr_el1, x0
|
||||
+
|
||||
+ /* Return to AArch32 Supervisor mode */
|
||||
+ mov x0, sp
|
||||
+ msr sp_el1, x0 /* Migrate SP */
|
||||
+ mrs x0, vbar_el2
|
||||
+ msr vbar_el1, x0 /* Migrate VBAR */
|
||||
+ mov x0, #0x1d3
|
||||
+ msr spsr_el2, x0
|
||||
+ msr elr_el2, x7
|
||||
+
|
||||
+ mov x0, #0
|
||||
+ mov x1, x8
|
||||
+ mov x2, x9
|
||||
+
|
||||
+ eret
|
||||
+ENDPROC(armv8_switch_to_el1_aarch32)
|
||||
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
|
||||
index 71b3108..0ecbcf7 100644
|
||||
--- a/arch/arm/include/asm/system.h
|
||||
+++ b/arch/arm/include/asm/system.h
|
||||
@@ -81,6 +81,8 @@ int __asm_flush_l3_cache(void);
|
||||
|
||||
void armv8_switch_to_el2(void);
|
||||
void armv8_switch_to_el1(void);
|
||||
+void armv8_switch_to_el2_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
|
||||
+void armv8_switch_to_el1_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
|
||||
void gic_init(void);
|
||||
void gic_send_sgi(unsigned long sgino);
|
||||
void wait_for_wakeup(void);
|
||||
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
|
||||
index a477cae..36f2cb0 100644
|
||||
--- a/arch/arm/lib/bootm.c
|
||||
+++ b/arch/arm/lib/bootm.c
|
||||
@@ -276,8 +276,24 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
||||
announce_and_cleanup(fake);
|
||||
|
||||
if (!fake) {
|
||||
- do_nonsec_virt_switch();
|
||||
- kernel_entry(images->ft_addr, NULL, NULL, NULL);
|
||||
+ if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
|
||||
+ (images->os.arch == IH_ARCH_ARM)) {
|
||||
+ smp_kick_all_cpus();
|
||||
+ dcache_disable();
|
||||
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
+ armv8_switch_to_el2();
|
||||
+ armv8_switch_to_el1_aarch32((u64)images->ep,
|
||||
+ (u64)gd->bd->bi_arch_number,
|
||||
+ (u64)images->ft_addr);
|
||||
+#else
|
||||
+ armv8_switch_to_el2_aarch32((u64)images->ep,
|
||||
+ (u64)gd->bd->bi_arch_number,
|
||||
+ (u64)images->ft_addr);
|
||||
+#endif
|
||||
+ } else {
|
||||
+ do_nonsec_virt_switch();
|
||||
+ kernel_entry(images->ft_addr, NULL, NULL, NULL);
|
||||
+ }
|
||||
}
|
||||
#else
|
||||
unsigned long machid = gd->bd->bi_arch_number;
|
||||
diff --git a/common/image-fit.c b/common/image-fit.c
|
||||
index c531ee7..0d54f71 100644
|
||||
--- a/common/image-fit.c
|
||||
+++ b/common/image-fit.c
|
||||
@@ -1144,7 +1144,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
|
||||
if (fit_image_get_arch(fit, noffset, &image_arch))
|
||||
return 0;
|
||||
return (arch == image_arch) ||
|
||||
- (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
|
||||
+ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) ||
|
||||
+ (arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1567,6 +1568,9 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
|
||||
int type_ok, os_ok;
|
||||
ulong load, data, len;
|
||||
uint8_t os;
|
||||
+#ifndef USE_HOSTCC
|
||||
+ uint8_t os_arch;
|
||||
+#endif
|
||||
const char *prop_name;
|
||||
int ret;
|
||||
|
||||
@@ -1650,6 +1654,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
|
||||
return -ENOEXEC;
|
||||
}
|
||||
#endif
|
||||
+
|
||||
+#ifndef USE_HOSTCC
|
||||
+ fit_image_get_arch(fit, noffset, &os_arch);
|
||||
+ images->os.arch = os_arch;
|
||||
+#endif
|
||||
+
|
||||
if (image_type == IH_TYPE_FLATDT &&
|
||||
!fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
|
||||
puts("FDT image is compressed");
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,141 +0,0 @@ |
||||
From 014f9196e18f4157232d0521f3a7502e7dbbb974 Mon Sep 17 00:00:00 2001
|
||||
From: Alison Wang <b18965@freescale.com>
|
||||
Date: Fri, 13 May 2016 13:28:07 +0800
|
||||
Subject: [PATCH 02/93] armv8: SMP support for loading 32-bit OS
|
||||
|
||||
Spin-table method is used for secondary cores to load 32-bit OS. The
|
||||
architecture information will be got through checking FIT image and
|
||||
saved in the os_arch element of spin-table, then the secondary cores
|
||||
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
|
||||
|
||||
Signed-off-by: Alison Wang <alison.wang@nxp.com>
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++++++++++++++++++++
|
||||
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++++++
|
||||
arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++++
|
||||
arch/arm/lib/bootm.c | 5 +++++
|
||||
4 files changed, 42 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
index 9c69ed1..93f4a65 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
@@ -13,6 +13,7 @@
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
+#include <asm/u-boot.h>
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
mov x29, lr /* Save LR */
|
||||
@@ -320,6 +321,11 @@ ENTRY(secondary_boot_func)
|
||||
gic_wait_for_interrupt_m x0, w1
|
||||
#endif
|
||||
|
||||
+ ldr x5, [x11, #24]
|
||||
+ ldr x6, =IH_ARCH_DEFAULT
|
||||
+ cmp x6, x5
|
||||
+ b.ne slave_cpu
|
||||
+
|
||||
bl secondary_switch_to_el2
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
bl secondary_switch_to_el1
|
||||
@@ -337,6 +343,21 @@ slave_cpu:
|
||||
tbz x1, #25, cpu_is_le
|
||||
rev x0, x0 /* BE to LE conversion */
|
||||
cpu_is_le:
|
||||
+
|
||||
+ ldr x5, [x11, #24]
|
||||
+ ldr x6, =IH_ARCH_DEFAULT
|
||||
+ cmp x6, x5
|
||||
+ b.eq 1f
|
||||
+
|
||||
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
+ bl secondary_switch_to_el2
|
||||
+ ldr x0, [x11]
|
||||
+ bl armv8_switch_to_el1_aarch32
|
||||
+#else
|
||||
+ bl armv8_switch_to_el2_aarch32
|
||||
+#endif
|
||||
+
|
||||
+1:
|
||||
br x0 /* branch to the given address */
|
||||
ENDPROC(secondary_boot_func)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
|
||||
index df7ffb8..dd91550 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
|
||||
@@ -22,6 +22,16 @@ phys_addr_t determine_mp_bootpg(void)
|
||||
return (phys_addr_t)&secondary_boot_code;
|
||||
}
|
||||
|
||||
+void update_os_arch_secondary_cores(uint8_t os_arch)
|
||||
+{
|
||||
+ u64 *table = get_spin_tbl_addr();
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 1; i < CONFIG_MAX_CPUS; i++)
|
||||
+ table[i * WORDS_PER_SPIN_TABLE_ENTRY +
|
||||
+ SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
|
||||
+}
|
||||
+
|
||||
int fsl_layerscape_wake_seconday_cores(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
|
||||
index e46e076..55f0e0c 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
|
||||
@@ -13,6 +13,7 @@
|
||||
* uint64_t entry_addr;
|
||||
* uint64_t status;
|
||||
* uint64_t lpid;
|
||||
+* uint64_t os_arch;
|
||||
* };
|
||||
* we pad this struct to 64 bytes so each entry is in its own cacheline
|
||||
* the actual spin table is an array of these structures
|
||||
@@ -20,6 +21,7 @@
|
||||
#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
|
||||
#define SPIN_TABLE_ELEM_STATUS_IDX 1
|
||||
#define SPIN_TABLE_ELEM_LPID_IDX 2
|
||||
+#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3
|
||||
#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
|
||||
#define SPIN_TABLE_ELEM_SIZE 64
|
||||
|
||||
@@ -35,4 +37,8 @@ phys_addr_t determine_mp_bootpg(void);
|
||||
void secondary_boot_func(void);
|
||||
int is_core_online(u64 cpu_id);
|
||||
#endif
|
||||
+
|
||||
+#define IH_ARCH_ARM 2 /* ARM */
|
||||
+#define IH_ARCH_ARM64 22 /* ARM64 */
|
||||
+
|
||||
#endif /* _FSL_LAYERSCAPE_MP_H */
|
||||
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
|
||||
index 36f2cb0..aae8c5b 100644
|
||||
--- a/arch/arm/lib/bootm.c
|
||||
+++ b/arch/arm/lib/bootm.c
|
||||
@@ -258,6 +258,10 @@ bool armv7_boot_nonsec(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
+__weak void update_os_arch_secondary_cores(uint8_t os_arch)
|
||||
+{
|
||||
+}
|
||||
+
|
||||
/* Subcommand: GO */
|
||||
static void boot_jump_linux(bootm_headers_t *images, int flag)
|
||||
{
|
||||
@@ -276,6 +280,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
||||
announce_and_cleanup(fake);
|
||||
|
||||
if (!fake) {
|
||||
+ update_os_arch_secondary_cores(images->os.arch);
|
||||
if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
|
||||
(images->os.arch == IH_ARCH_ARM)) {
|
||||
smp_kick_all_cpus();
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,30 +0,0 @@ |
||||
From f9e93719a99120e93628bf39bd997164a01afda2 Mon Sep 17 00:00:00 2001
|
||||
From: Alison Wang <b18965@freescale.com>
|
||||
Date: Fri, 13 May 2016 15:23:27 +0800
|
||||
Subject: [PATCH 03/93] armv8: aarch32: Disable CONFIG_FSL_LS_PPA for loading
|
||||
32-bit OS
|
||||
|
||||
The current U-Boot doesn't support loading 32-bit OS with PPA, so
|
||||
disable CONFIG_FSL_LS_PPA so far.
|
||||
|
||||
Signed-off-by: Alison Wang <alison.wang@nxp.com>
|
||||
---
|
||||
include/configs/ls1043ardb.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
|
||||
index c1abc73..af8b441 100644
|
||||
--- a/include/configs/ls1043ardb.h
|
||||
+++ b/include/configs/ls1043ardb.h
|
||||
@@ -9,7 +9,7 @@
|
||||
|
||||
#include "ls1043a_common.h"
|
||||
|
||||
-#define CONFIG_FSL_LS_PPA
|
||||
+#undef CONFIG_FSL_LS_PPA
|
||||
#if defined(CONFIG_FSL_LS_PPA)
|
||||
#define CONFIG_ARMV8_PSCI
|
||||
#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,31 +0,0 @@ |
||||
From cb5a037831053d22ce260dbec6b378f532bd2c6c Mon Sep 17 00:00:00 2001
|
||||
From: Alison Wang <b18965@freescale.com>
|
||||
Date: Tue, 21 Jun 2016 17:14:35 +0800
|
||||
Subject: [PATCH 04/93] armv8: Support loading 32-bit OS which is not in the
|
||||
form of FIT
|
||||
|
||||
As only FIT image is supported now, this patch is to support loading
|
||||
32-bit uImage, dtb and rootfs separately.
|
||||
|
||||
Signed-off-by: Alison Wang <alison.wang@nxp.com>
|
||||
---
|
||||
include/image.h | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/image.h b/include/image.h
|
||||
index 299d6d2..0ea5f8e 100644
|
||||
--- a/include/image.h
|
||||
+++ b/include/image.h
|
||||
@@ -694,7 +694,8 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type)
|
||||
}
|
||||
static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
|
||||
{
|
||||
- return (image_get_arch(hdr) == arch);
|
||||
+ return (image_get_arch(hdr) == arch) ||
|
||||
+ (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
|
||||
}
|
||||
static inline int image_check_os(const image_header_t *hdr, uint8_t os)
|
||||
{
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,68 +0,0 @@ |
||||
From 3c22f3fcbdb9f919ebdfa87a2ec237ac2abb7e03 Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Thu, 27 Oct 2016 23:45:45 +0800
|
||||
Subject: [PATCH 05/93] armv8: set openwrt/lede default boot env for
|
||||
ls1043ardb
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
include/configs/ls1043a_common.h | 28 +++++++++++++++++++++++++---
|
||||
1 file changed, 25 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
|
||||
index 68678f3..1db05bb 100644
|
||||
--- a/include/configs/ls1043a_common.h
|
||||
+++ b/include/configs/ls1043a_common.h
|
||||
@@ -273,6 +273,16 @@
|
||||
"5m(kernel),1m(dtb),9m(file_system)"
|
||||
#endif
|
||||
|
||||
+#define WRTBOOT_DEFAULT "setenv bootargs root=/dev/mtdblock6 " \
|
||||
+ "rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 " \
|
||||
+ "console=ttyS0,115200 mtdparts=60000000.nor:1M(rcw),1M(u-boot)," \
|
||||
+ "1M(u-boot-env),1M(fman),1M(dtb),5M(kernel),54M(rootfs),64M(otherbank)" \
|
||||
+ " && cp.b 60400000 $fdtaddr 100000 && cp.b 60500000 $loadaddr 500000" \
|
||||
+ " && bootm $loadaddr - $fdtaddr"
|
||||
+#define WRTUPDATE_DEFAULT "tftp a0000000 <tftp_folder>/" \
|
||||
+ "lede-layerscape-64b-ls1043ardb-squashfs-firmware.bin && protect off all" \
|
||||
+ " && erase 60000000 +4000000 && cp.b a0000000 60000000 $filesize && reset"
|
||||
+
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
@@ -286,6 +296,19 @@
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
"console=ttyAMA0,38400n8\0" \
|
||||
+ "ethaddr=00:e0:0c:00:77:00\0" \
|
||||
+ "eth1addr=00:e0:0c:00:77:01\0" \
|
||||
+ "eth2addr=00:e0:0c:00:77:02\0" \
|
||||
+ "eth3addr=00:e0:0c:00:77:03\0" \
|
||||
+ "eth4addr=00:e0:0c:00:77:04\0" \
|
||||
+ "eth5addr=00:e0:0c:00:77:05\0" \
|
||||
+ "eth6addr=00:e0:0c:00:77:06\0" \
|
||||
+ "ethact=FM1@DTSEC2\0" \
|
||||
+ "loadaddr=82000000\0" \
|
||||
+ "ramdiskaddr=88000000\0" \
|
||||
+ "fdtaddr=8f000000\0" \
|
||||
+ "wrtboot=" WRTBOOT_DEFAULT "\0" \
|
||||
+ "wrtupdate=" WRTUPDATE_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0"
|
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
|
||||
@@ -296,10 +319,9 @@
|
||||
#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
|
||||
"e0000 f00000 && bootm $kernel_load"
|
||||
#else
|
||||
-#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
|
||||
- "$kernel_size && bootm $kernel_load"
|
||||
+#define CONFIG_BOOTCOMMAND "run wrtboot"
|
||||
#endif
|
||||
-#define CONFIG_BOOTDELAY 10
|
||||
+#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,37 +0,0 @@ |
||||
From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Tue, 15 Mar 2016 13:40:07 +0530
|
||||
Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in
|
||||
SMMU_BASE
|
||||
|
||||
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
|
||||
LS1012A are layerscape SoC without SMMU IP.
|
||||
|
||||
So put SMMU configuration code under SMMU_BASE.
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
index 93f4a65..5f5bfb9 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
@@ -95,11 +95,13 @@ ENTRY(lowlevel_init)
|
||||
bl ccn504_set_qos
|
||||
#endif
|
||||
|
||||
+#ifdef SMMU_BASE
|
||||
/* Set the SMMU page size in the sACR register */
|
||||
ldr x1, =SMMU_BASE
|
||||
ldr w0, [x1, #0x10]
|
||||
orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
|
||||
str w0, [x1, #0x10]
|
||||
+#endif
|
||||
|
||||
/* Initialize GIC Secure Bank Status */
|
||||
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,44 +0,0 @@ |
||||
From 825d623c913c63b1f00c42f27ef0916b11d9f09f Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Tue, 15 Mar 2016 13:40:22 +0530
|
||||
Subject: [PATCH 07/93] armv8: fsl-layerscape: Avoid LS1043A specifc defines
|
||||
|
||||
Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
|
||||
|
||||
So Avoid LS1043A specific defines in arch/arm
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
|
||||
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
index 92dcb72..23f0c88 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
@@ -314,7 +314,7 @@ int sata_init(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
-#elif defined(CONFIG_LS1043A)
|
||||
+#elif defined(CONFIG_FSL_LSCH2)
|
||||
#ifdef CONFIG_SCSI_AHCI_PLAT
|
||||
int sata_init(void)
|
||||
{
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
|
||||
index d1fbde7..7096dac 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
|
||||
@@ -55,7 +55,7 @@ enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
-#elif defined(CONFIG_LS1043A)
|
||||
+#elif defined(CONFIG_FSL_LSCH2)
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,82 +0,0 @@ |
||||
From b3bbf1aeb0245a0f5565f669dd4b2f5f5be40d8a Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Wed, 16 Mar 2016 08:43:55 +0530
|
||||
Subject: [PATCH 08/93] armv8/ls1043a: Add the OCRAM initialization
|
||||
|
||||
Clear the content to zero and the ECC error bit of OCRAM1/2.
|
||||
|
||||
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
|
||||
accessing it, or else it will generate ECC error. And the IBR has
|
||||
accessed the OCRAM before this initialization, so the ECC error
|
||||
status bit should to be cleared.
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 39 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
|
||||
index dd583c9..235213f 100644
|
||||
--- a/arch/arm/cpu/armv8/start.S
|
||||
+++ b/arch/arm/cpu/armv8/start.S
|
||||
@@ -11,6 +11,9 @@
|
||||
#include <asm/macro.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
|
||||
+#define DCSR_SYS_DCFG_SBEESR2 0x20140534
|
||||
+#define DCSR_SYS_DCFG_MBEESR2 0x20140544
|
||||
+
|
||||
/*************************************************************************
|
||||
*
|
||||
* Startup Code (reset vector)
|
||||
@@ -215,10 +218,46 @@ WEAK(lowlevel_init)
|
||||
#endif /* CONFIG_ARMV8_MULTIENTRY */
|
||||
|
||||
2:
|
||||
+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
|
||||
+ bl fsl_ocram_init
|
||||
+#endif
|
||||
mov lr, x29 /* Restore LR */
|
||||
ret
|
||||
ENDPROC(lowlevel_init)
|
||||
|
||||
+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
|
||||
+ENTRY(fsl_ocram_init)
|
||||
+ mov x28, lr /* Save LR */
|
||||
+ bl fsl_clear_ocram
|
||||
+ bl fsl_ocram_clear_ecc_err
|
||||
+ mov lr, x28 /* Restore LR */
|
||||
+ ret
|
||||
+ENDPROC(fsl_ocram_init)
|
||||
+
|
||||
+ENTRY(fsl_clear_ocram)
|
||||
+/* Clear OCRAM */
|
||||
+ ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
|
||||
+ ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
|
||||
+ mov x2, #0
|
||||
+clear_loop:
|
||||
+ str x2, [x0]
|
||||
+ add x0, x0, #8
|
||||
+ cmp x0, x1
|
||||
+ b.lo clear_loop
|
||||
+ ret
|
||||
+ENDPROC(fsl_clear_ocram)
|
||||
+
|
||||
+ENTRY(fsl_ocram_clear_ecc_err)
|
||||
+ /* OCRAM1/2 ECC status bit */
|
||||
+ mov w1, #0x60
|
||||
+ ldr x0, =DCSR_SYS_DCFG_SBEESR2
|
||||
+ str w1, [x0]
|
||||
+ ldr x0, =DCSR_SYS_DCFG_MBEESR2
|
||||
+ str w1, [x0]
|
||||
+ ret
|
||||
+ENDPROC(fsl_ocram_init)
|
||||
+#endif
|
||||
+
|
||||
WEAK(smp_kick_all_cpus)
|
||||
/* Kick secondary cpus up by SGI 0 interrupt */
|
||||
mov x29, lr /* Save LR */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,29 +0,0 @@ |
||||
From f022d8d9dc505ee917fef6c7109d67cc015a98fa Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Mon, 25 Apr 2016 16:05:36 +0530
|
||||
Subject: [PATCH 09/93] driver: mtd: spi: Adding support for QSPI Emulator
|
||||
|
||||
Serial number and vendor id are added for The QSPI Emulator
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/sf_params.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
|
||||
index 4f37e33..1424f2a 100644
|
||||
--- a/drivers/mtd/spi/sf_params.c
|
||||
+++ b/drivers/mtd/spi/sf_params.c
|
||||
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
|
||||
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
|
||||
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
|
||||
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
|
||||
+ {"S25FS512S", 0x010220, 0x0102, 256 * 1024, 256, RD_FULL, WR_QPP},
|
||||
{"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
|
||||
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
|
||||
{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,45 +0,0 @@ |
||||
From 27d1d5620ae352d230189fbea364198398065ae2 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Mon, 25 Apr 2016 16:06:48 +0530
|
||||
Subject: [PATCH 10/93] driver: mtd: spi: Adding support for QSPI flash
|
||||
|
||||
Serial number and vendor id are added for QSPI flash
|
||||
common on both LS1012AQDS and LS1012ARDB.
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/sf_params.c | 1 +
|
||||
drivers/mtd/spi/spi_flash.c | 3 ++-
|
||||
2 files changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
|
||||
index 1424f2a..1afb8b3 100644
|
||||
--- a/drivers/mtd/spi/sf_params.c
|
||||
+++ b/drivers/mtd/spi/sf_params.c
|
||||
@@ -68,6 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
|
||||
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
|
||||
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
|
||||
{"S25FS512S", 0x010220, 0x0102, 256 * 1024, 256, RD_FULL, WR_QPP},
|
||||
+ {"S25FS512S_256K", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
|
||||
{"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
|
||||
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
|
||||
{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index 2d23aee..865e929 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -1033,7 +1033,8 @@ int spi_flash_scan(struct spi_flash *flash)
|
||||
* sector that is not overlaid by the parameter sectors.
|
||||
* The uniform sector erase command has no effect on parameter sectors.
|
||||
*/
|
||||
- if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
|
||||
+ if ((jedec == 0x0219 || (jedec == 0x0220)) &&
|
||||
+ (ext_jedec & 0xff00) == 0x4d00) {
|
||||
int ret;
|
||||
u8 id[6];
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,38 +0,0 @@ |
||||
From 5a5108627b16ab33fb82c16e49ac926ef3a901b8 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Wed, 6 Apr 2016 17:44:22 +0530
|
||||
Subject: [PATCH 11/93] armv8: fsl-layerscape: fix compile warning "rcw_tmp"
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
|
||||
‘get_sys_info’:
|
||||
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
|
||||
unused variable ‘rcw_tmp’ [-Wunused-variable]
|
||||
u32 rcw_tmp;
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 ++++-
|
||||
1 file changed, 4 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
index d301fff..078b087 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
|
||||
u32 ccr;
|
||||
#endif
|
||||
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
|
||||
+#if (defined(CONFIG_FSL_ESDHC) &&\
|
||||
+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
|
||||
+ defined(CONFIG_SYS_DPAA_FMAN)
|
||||
+
|
||||
u32 rcw_tmp;
|
||||
#endif
|
||||
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,58 +0,0 @@ |
||||
From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Sat, 23 Apr 2016 12:34:59 +0530
|
||||
Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS
|
||||
attribute
|
||||
|
||||
When switching between the early and final mmu tables, the stack will
|
||||
get corrupted if the Non-Secure attribute is different. For ls1043a,
|
||||
this issue is currently masked because flush_dcache_all is called
|
||||
before the switch when CONFIG_SYS_DPAA_FMAN is defined.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++----
|
||||
1 file changed, 8 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
index a9dadfa..a7522da 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
@@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
|
||||
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
|
||||
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
|
||||
+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
|
||||
+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
|
||||
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
|
||||
+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
|
||||
@@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
|
||||
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
|
||||
- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
|
||||
+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,418 +0,0 @@ |
||||
From 53ffd67d944fa23037e7f97e583fae300d4367f7 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Sat, 23 Apr 2016 15:23:52 +0530
|
||||
Subject: [PATCH 13/93] armv8: fsl-layerscape: Add support of QorIQ LS1012A
|
||||
SoC
|
||||
|
||||
[context adjustment]
|
||||
|
||||
The QorIQ LS1012A processor, optimized for battery-backed or
|
||||
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
|
||||
packet forwarding engine and high-speed interfaces to deliver
|
||||
line-rate networking performance.
|
||||
|
||||
This patch add support of LS1012A SoC along with
|
||||
- Update platform & DDR clock read logic as per SVR
|
||||
- Define MMDC controller register set.
|
||||
- Update LUT base address for PCIe
|
||||
- Avoid L3 platform cache compilation
|
||||
- Update USB address, errata
|
||||
- SerDes table
|
||||
|
||||
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 ++
|
||||
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 24 +++++--
|
||||
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +
|
||||
arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 74 ++++++++++++++++++++
|
||||
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +-
|
||||
arch/arm/include/asm/arch-fsl-layerscape/config.h | 32 +++++++++
|
||||
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 +
|
||||
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++
|
||||
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
|
||||
include/fsl_mmdc.h | 53 ++++++++++++++
|
||||
include/linux/usb/xhci-fsl.h | 4 ++
|
||||
12 files changed, 199 insertions(+), 7 deletions(-)
|
||||
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
|
||||
create mode 100644 include/fsl_mmdc.h
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
|
||||
index 27bfeb1..03f73d1 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
|
||||
@@ -33,3 +33,7 @@ endif
|
||||
ifneq ($(CONFIG_LS1043A),)
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
|
||||
endif
|
||||
+
|
||||
+ifneq ($(CONFIG_LS1012A),)
|
||||
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
|
||||
+endif
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
index 078b087..63e5bed 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
@@ -33,6 +33,7 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
#endif
|
||||
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
|
||||
unsigned int cpu;
|
||||
+ unsigned int svr, ver;
|
||||
const u8 core_cplx_pll[8] = {
|
||||
[0] = 0, /* CC1 PPL / 1 */
|
||||
[1] = 0, /* CC1 PPL / 2 */
|
||||
@@ -59,12 +60,20 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
||||
- sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
- FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
- FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
- sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
- FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
- FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
+ svr = gur_in32(&gur->svr);
|
||||
+ ver = SVR_SOC_VER(svr);
|
||||
+ if (ver == SVR_LS1012) {
|
||||
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
+ } else {
|
||||
+ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
+ }
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
|
||||
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
|
||||
@@ -83,6 +92,9 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
|
||||
+ if (ver == SVR_LS1012)
|
||||
+ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
|
||||
+
|
||||
#define HWA_CGA_M1_CLK_SEL 0xe0000000
|
||||
#define HWA_CGA_M1_CLK_SHIFT 29
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
index 5f5bfb9..b40834a 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
||||
@@ -184,6 +184,7 @@ ENTRY(lowlevel_init)
|
||||
ret
|
||||
ENDPROC(lowlevel_init)
|
||||
|
||||
+#ifdef CONFIG_FSL_LSCH3
|
||||
hnf_pstate_poll:
|
||||
/* x0 has the desired status, return 0 for success, 1 for timeout
|
||||
* clobber x1, x2, x3, x4, x6, x7
|
||||
@@ -261,6 +262,7 @@ ENTRY(__asm_flush_l3_cache)
|
||||
mov lr, x29
|
||||
ret
|
||||
ENDPROC(__asm_flush_l3_cache)
|
||||
+#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
/* Keep literals not used by the secondary boot code outside it */
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
|
||||
new file mode 100644
|
||||
index 0000000..ff0903c
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
|
||||
@@ -0,0 +1,74 @@
|
||||
+/*
|
||||
+ * Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <asm/arch/fsl_serdes.h>
|
||||
+#include <asm/arch/immap_lsch2.h>
|
||||
+
|
||||
+struct serdes_config {
|
||||
+ u32 protocol;
|
||||
+ u8 lanes[SRDS_MAX_LANES];
|
||||
+};
|
||||
+
|
||||
+static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
+ {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
|
||||
+ {0x0008, {NONE, NONE, NONE, SATA1} },
|
||||
+ {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
|
||||
+ {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
|
||||
+ {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
|
||||
+ {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
|
||||
+ {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
|
||||
+ {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
|
||||
+ {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
|
||||
+ {}
|
||||
+};
|
||||
+
|
||||
+static struct serdes_config *serdes_cfg_tbl[] = {
|
||||
+ serdes1_cfg_tbl,
|
||||
+};
|
||||
+
|
||||
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
+{
|
||||
+ struct serdes_config *ptr;
|
||||
+
|
||||
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
+ return 0;
|
||||
+
|
||||
+ ptr = serdes_cfg_tbl[serdes];
|
||||
+ while (ptr->protocol) {
|
||||
+ if (ptr->protocol == cfg)
|
||||
+ return ptr->lanes[lane];
|
||||
+ ptr++;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct serdes_config *ptr;
|
||||
+
|
||||
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
+ return 0;
|
||||
+
|
||||
+ ptr = serdes_cfg_tbl[serdes];
|
||||
+ while (ptr->protocol) {
|
||||
+ if (ptr->protocol == prtcl)
|
||||
+ break;
|
||||
+ ptr++;
|
||||
+ }
|
||||
+
|
||||
+ if (!ptr->protocol)
|
||||
+ return 0;
|
||||
+
|
||||
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
+ if (ptr->lanes[i] != NONE)
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
index 23f0c88..ec561a7 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
@@ -12,8 +12,10 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/arch-fsl-layerscape/config.h>
|
||||
+#ifdef CONFIG_SYS_FSL_DDR
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr.h>
|
||||
+#endif
|
||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||
#include <fsl_validate.h>
|
||||
#endif
|
||||
@@ -46,14 +48,16 @@ static void erratum_a009008(void)
|
||||
static void erratum_a009798(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
|
||||
-#if defined(CONFIG_LS1043A)
|
||||
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
|
||||
u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
|
||||
scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
|
||||
+#if defined(CONFIG_LS1043A)
|
||||
val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
|
||||
scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
|
||||
val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
|
||||
scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
|
||||
+#endif
|
||||
#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
|
||||
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
|
||||
u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
index f876c56..6ea4e8e 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
@@ -14,8 +14,11 @@
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
|
||||
#endif
|
||||
+
|
||||
+#ifndef CONFIG_LS1012A
|
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* Reserve secure memory
|
||||
@@ -205,6 +208,35 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008997
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009007
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
+#elif defined(CONFIG_LS1012A)
|
||||
+#define CONFIG_MAX_CPUS 1
|
||||
+#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
+#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
|
||||
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
||||
+#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
+
|
||||
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
|
||||
+
|
||||
+#define GICD_BASE 0x01401000
|
||||
+#define GICC_BASE 0x01402000
|
||||
+
|
||||
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
||||
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
+#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
+#define CONFIG_SYS_FSL_WDOG_BE
|
||||
+#define CONFIG_SYS_FSL_DSPI_BE
|
||||
+#define CONFIG_SYS_FSL_QSPI_BE
|
||||
+#define CONFIG_SYS_FSL_PEX_LUT_BE
|
||||
+
|
||||
+#define SRDS_MAX_LANES 4
|
||||
+#define CONFIG_SYS_FSL_SRDS_1
|
||||
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
+#define CONFIG_SYS_FSL_SEC_BE
|
||||
+
|
||||
+#define CONFIG_SYS_FSL_ERRATUM_A009798
|
||||
+
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
index a7522da..e4ff990 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
|
||||
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
|
||||
CPU_TYPE_ENTRY(LS1023, LS1023, 2),
|
||||
CPU_TYPE_ENTRY(LS2040, LS2040, 4),
|
||||
+ CPU_TYPE_ENTRY(LS1012, LS1012, 1),
|
||||
};
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
|
||||
index 7096dac..4a3f4f3 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
|
||||
@@ -134,6 +134,7 @@ enum srds_prtcl {
|
||||
SGMII_2500_FM2_DTSEC6,
|
||||
SGMII_2500_FM2_DTSEC9,
|
||||
SGMII_2500_FM2_DTSEC10,
|
||||
+ TX_CLK,
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index 2852f9c..5b026f8 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -62,7 +62,11 @@
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
|
||||
/* LUT registers */
|
||||
+#ifdef CONFIG_LS1012A
|
||||
+#define PCIE_LUT_BASE 0xC0000
|
||||
+#else
|
||||
#define PCIE_LUT_BASE 0x10000
|
||||
+#endif
|
||||
#define PCIE_LUT_LCTRL0 0x7F8
|
||||
#define PCIE_LUT_DBG 0x7FC
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
|
||||
index 56989e1..0822b49 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
|
||||
@@ -41,6 +41,7 @@ struct cpu_type {
|
||||
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
|
||||
|
||||
#define SVR_WO_E 0xFFFFFE
|
||||
+#define SVR_LS1012 0x870400
|
||||
#define SVR_LS1043 0x879200
|
||||
#define SVR_LS1023 0x879208
|
||||
#define SVR_LS2045 0x870120
|
||||
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
|
||||
new file mode 100644
|
||||
index 0000000..3df822e
|
||||
--- /dev/null
|
||||
+++ b/include/fsl_mmdc.h
|
||||
@@ -0,0 +1,53 @@
|
||||
+/*
|
||||
+ * Copyright 2015 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef FSL_MMDC_H
|
||||
+#define FSL_MMDC_H
|
||||
+
|
||||
+/* MMDC Registers */
|
||||
+struct mmdc_p_regs {
|
||||
+ u32 mdctl;
|
||||
+ u32 mdpdc;
|
||||
+ u32 mdotc;
|
||||
+ u32 mdcfg0;
|
||||
+ u32 mdcfg1;
|
||||
+ u32 mdcfg2;
|
||||
+ u32 mdmisc;
|
||||
+ u32 mdscr;
|
||||
+ u32 mdref;
|
||||
+ u32 res1[2];
|
||||
+ u32 mdrwd;
|
||||
+ u32 mdor;
|
||||
+ u32 mdmrr;
|
||||
+ u32 mdcfg3lp;
|
||||
+ u32 mdmr4;
|
||||
+ u32 mdasp;
|
||||
+ u32 res3[239];
|
||||
+ u32 maarcr;
|
||||
+ u32 mapsr;
|
||||
+ u32 res4[254];
|
||||
+ u32 mpzqhwctrl;
|
||||
+ u32 res5[2];
|
||||
+ u32 mpwldectrl0;
|
||||
+ u32 mpwldectrl1;
|
||||
+ u32 res6;
|
||||
+ u32 mpodtctrl;
|
||||
+ u32 mprddqby0dl;
|
||||
+ u32 mprddqby1dl;
|
||||
+ u32 mprddqby2dl;
|
||||
+ u32 mprddqby3dl;
|
||||
+ u32 res7[4];
|
||||
+ u32 mpdgctrl0;
|
||||
+ u32 mpdgctrl1;
|
||||
+ u32 res8;
|
||||
+ u32 mprddlctl;
|
||||
+ u32 res9;
|
||||
+ u32 mpwrdlctl;
|
||||
+ u32 res10[25];
|
||||
+ u32 mpmur0;
|
||||
+};
|
||||
+
|
||||
+#endif /* FSL_MMDC_H */
|
||||
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
|
||||
index 4966608..72a5d5b 100644
|
||||
--- a/include/linux/usb/xhci-fsl.h
|
||||
+++ b/include/linux/usb/xhci-fsl.h
|
||||
@@ -66,6 +66,10 @@ struct fsl_xhci {
|
||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
|
||||
+#elif defined(CONFIG_LS1012A)
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
#endif
|
||||
|
||||
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,634 +0,0 @@ |
||||
From 4bb641f4d28053bd1ff4af73dc0a63be2151f851 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Mon, 25 Apr 2016 14:37:33 +0530
|
||||
Subject: [PATCH 15/93] armv8: ls1012a: Add support of ls1012ardb board
|
||||
|
||||
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
|
||||
development platform, with a complete debugging environment.
|
||||
The LS1012ARDB board supports the QorIQ LS1012A processor and is
|
||||
optimized to support the high-bandwidth DDR3L memory and
|
||||
a full complement of high-speed SerDes ports.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/Kconfig | 10 ++
|
||||
arch/arm/dts/Makefile | 3 +-
|
||||
arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++
|
||||
arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++
|
||||
board/freescale/ls1012ardb/Kconfig | 15 +++
|
||||
board/freescale/ls1012ardb/MAINTAINERS | 6 +
|
||||
board/freescale/ls1012ardb/Makefile | 7 +
|
||||
board/freescale/ls1012ardb/README | 89 +++++++++++++
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 220 +++++++++++++++++++++++++++++++
|
||||
configs/ls1012ardb_qspi_defconfig | 10 ++
|
||||
include/configs/ls1012a_common.h | 3 +-
|
||||
include/configs/ls1012ardb.h | 61 +++++++++
|
||||
include/linux/usb/xhci-fsl.h | 2 +-
|
||||
13 files changed, 477 insertions(+), 4 deletions(-)
|
||||
create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
|
||||
create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
|
||||
create mode 100644 board/freescale/ls1012ardb/Kconfig
|
||||
create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
|
||||
create mode 100644 board/freescale/ls1012ardb/Makefile
|
||||
create mode 100644 board/freescale/ls1012ardb/README
|
||||
create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
|
||||
create mode 100644 configs/ls1012ardb_qspi_defconfig
|
||||
create mode 100644 include/configs/ls1012ardb.h
|
||||
|
||||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
|
||||
index f5033db..5c20801 100644
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -656,6 +656,15 @@ config TARGET_LS1012AQDS
|
||||
development platform that supports the QorIQ LS1012A
|
||||
Layerscape Architecture processor.
|
||||
|
||||
+config TARGET_LS1012ARDB
|
||||
+ bool "Support ls1012ardb"
|
||||
+ select ARM64
|
||||
+ help
|
||||
+ Support for Freescale LS1012ARDB platform.
|
||||
+ The LS1012A Reference design board (RDB) is a high-performance
|
||||
+ development platform that supports the QorIQ LS1012A
|
||||
+ Layerscape Architecture processor.
|
||||
+
|
||||
config TARGET_LS1021AQDS
|
||||
bool "Support ls1021aqds"
|
||||
select CPU_V7
|
||||
@@ -802,6 +811,7 @@ source "board/freescale/ls1043aqds/Kconfig"
|
||||
source "board/freescale/ls1021atwr/Kconfig"
|
||||
source "board/freescale/ls1043ardb/Kconfig"
|
||||
source "board/freescale/ls1012aqds/Kconfig"
|
||||
+source "board/freescale/ls1012ardb/Kconfig"
|
||||
source "board/freescale/mx23evk/Kconfig"
|
||||
source "board/freescale/mx25pdk/Kconfig"
|
||||
source "board/freescale/mx28evk/Kconfig"
|
||||
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
|
||||
index ed5eb38..9e8137b 100644
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -95,7 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
|
||||
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
|
||||
fsl-ls1043a-qds-lpuart.dtb \
|
||||
fsl-ls1043a-rdb.dtb \
|
||||
- fsl-ls1012a-qds.dtb
|
||||
+ fsl-ls1012a-qds.dtb \
|
||||
+ fsl-ls1012a-rdb.dtb
|
||||
|
||||
dtb-$(CONFIG_MACH_SUN4I) += \
|
||||
sun4i-a10-a1000.dtb \
|
||||
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
|
||||
new file mode 100644
|
||||
index 0000000..4ec9786
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
|
||||
@@ -0,0 +1,16 @@
|
||||
+/*
|
||||
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
|
||||
+ *
|
||||
+ * Copyright (C) 2016, Freescale Semiconductor
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "fsl-ls1012a-rdb.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &duart0;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
|
||||
new file mode 100644
|
||||
index 0000000..71aba78
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
|
||||
@@ -0,0 +1,39 @@
|
||||
+/*
|
||||
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
|
||||
+ *
|
||||
+ * Copyright (C) 2016, Freescale Semiconductor
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+
|
||||
+/include/ "fsl-ls1012a.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "LS1012A RDB Board";
|
||||
+ aliases {
|
||||
+ spi0 = &qspi;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&qspi {
|
||||
+ bus-num = <0>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ qflash0: s25fl128s@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "spi-flash";
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&duart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000..3f67c28
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012ardb/Kconfig
|
||||
@@ -0,0 +1,15 @@
|
||||
+if TARGET_LS1012ARDB
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "ls1012ardb"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "freescale"
|
||||
+
|
||||
+config SYS_SOC
|
||||
+ default "fsl-layerscape"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "ls1012ardb"
|
||||
+
|
||||
+endif
|
||||
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
|
||||
new file mode 100644
|
||||
index 0000000..757e810
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012ardb/MAINTAINERS
|
||||
@@ -0,0 +1,6 @@
|
||||
+LS1012ARDB BOARD
|
||||
+M:
|
||||
+S: Maintained
|
||||
+F: board/freescale/ls1012ardb/
|
||||
+F: include/configs/ls1012ardb.h
|
||||
+F: configs/ls1012ardb_defconfig
|
||||
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
|
||||
new file mode 100644
|
||||
index 0000000..05fa9d9
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012ardb/Makefile
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+obj-y += ls1012ardb.o
|
||||
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
|
||||
new file mode 100644
|
||||
index 0000000..cda03f6
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012ardb/README
|
||||
@@ -0,0 +1,89 @@
|
||||
+Overview
|
||||
+--------
|
||||
+The LS1012ARDB power supplies (PS) provide all the voltages necessary
|
||||
+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
|
||||
+and other onboard peripherals.
|
||||
+
|
||||
+LS1012A SoC Overview
|
||||
+--------------------
|
||||
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
|
||||
+A53 processor, with 32 KB of parity protected L1-I cache,
|
||||
+32 KB of ECC protected L1-D cache, as well as 256 KB of
|
||||
+ECC protected L2 cache.
|
||||
+
|
||||
+The LS1012A SoC includes the following function and features:
|
||||
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
|
||||
+ - ARM v8 cryptography extensions
|
||||
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
|
||||
+ 16-/8-bit operation (no ECC support)
|
||||
+ - ARM core-link CCI-400 cache coherent interconnect
|
||||
+ - Packet Forwarding Engine (PFE)
|
||||
+ - Cryptography acceleration (SEC)
|
||||
+ - Ethernet interfaces supported by PFE:
|
||||
+ - One Configurable x3 SerDes:
|
||||
+ Two Serdes PLLs supported for usage by any SerDes data lane
|
||||
+ Support for up to 6 GBaud operation
|
||||
+ - High-speed peripheral interfaces:
|
||||
+ - One PCI Express Gen2 controller, supporting x1 operation
|
||||
+ - One serial ATA (SATA Gen 3.0) controller
|
||||
+ - One USB 3.0/2.0 controller with integrated PHY
|
||||
+ - One USB 2.0 controller with ULPI interface. .
|
||||
+ - Additional peripheral interfaces:
|
||||
+ - One quad serial peripheral interface (QuadSPI) controller
|
||||
+ - One serial peripheral interface (SPI) controller
|
||||
+ - Two enhanced secure digital host controllers
|
||||
+ - Two I2C controllers
|
||||
+ - One 16550 compliant DUART (two UART interfaces)
|
||||
+ - Two general purpose IOs (GPIO)
|
||||
+ - Two FlexTimers
|
||||
+ - Five synchronous audio interfaces (SAI)
|
||||
+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
|
||||
+ - Single-source clocking solution enabling generation of core, platform,
|
||||
+ DDR, SerDes, and USB clocks from a single external crystal and internal
|
||||
+ crystaloscillator
|
||||
+ - Thermal monitor unit (TMU) with +/- 3C accuracy
|
||||
+ - Two WatchDog timers
|
||||
+ - ARM generic timer
|
||||
+ - QorIQ platform's trust architecture 2.1
|
||||
+
|
||||
+ LS1012ARDB board Overview
|
||||
+ -----------------------
|
||||
+ - SERDES Connections, 4 lanes supporting:
|
||||
+ - PCI Express - 3.0
|
||||
+ - SGMII, SGMII 2.5
|
||||
+ - SATA 3.0
|
||||
+ - DDR Controller
|
||||
+ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
|
||||
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
|
||||
+ signals to
|
||||
+ - QSPI NOR flash memory (2 virtual banks)
|
||||
+ - the QSPI emulator.s
|
||||
+ - USB 3.0
|
||||
+ - one high-speed USB 2.0/3.0 port.
|
||||
+ - Two enhanced secure digital host controllers:
|
||||
+ - SDHC1 controller can be connected to onboard SDHC connector
|
||||
+ - SDHC2 controller: Three dual 1:4 mux/demux devices,
|
||||
+ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
|
||||
+ SDIO WiFi, SPI, and Ardiuno shield
|
||||
+ - 2 I2C controllers
|
||||
+ - One SATA onboard connectors
|
||||
+ - UART
|
||||
+ - The LS1012A processor consists of two UART controllers,
|
||||
+ out of which only UART1 is used on RDB.
|
||||
+ - ARM JTAG support
|
||||
+
|
||||
+Booting Options
|
||||
+---------------
|
||||
+a) QSPI Flash Emu Boot
|
||||
+b) QSPI Flash 1
|
||||
+c) QSPI Flash 2
|
||||
+
|
||||
+QSPI flash map
|
||||
+--------------
|
||||
+Images | Size |QSPI Flash Address
|
||||
+------------------------------------------
|
||||
+RCW + PBI | 1MB | 0x4000_0000
|
||||
+U-boot | 1MB | 0x4010_0000
|
||||
+U-boot Env | 1MB | 0x4020_0000
|
||||
+PPA FIT image | 2MB | 0x4050_0000
|
||||
+Linux ITB | ~53MB | 0x40A0_0000
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
new file mode 100644
|
||||
index 0000000..4a7aaaa
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -0,0 +1,220 @@
|
||||
+/*
|
||||
+ * Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <i2c.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <asm/arch/clock.h>
|
||||
+#include <asm/arch/fsl_serdes.h>
|
||||
+#include <asm/arch/ppa.h>
|
||||
+#include <asm/arch/soc.h>
|
||||
+#include <hwconfig.h>
|
||||
+#include <ahci.h>
|
||||
+#include <mmc.h>
|
||||
+#include <scsi.h>
|
||||
+#include <fsl_csu.h>
|
||||
+#include <fsl_esdhc.h>
|
||||
+#include <environment.h>
|
||||
+#include <fsl_mmdc.h>
|
||||
+#include <netdev.h>
|
||||
+
|
||||
+DECLARE_GLOBAL_DATA_PTR;
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ u8 in1;
|
||||
+
|
||||
+ puts("Board: LS1012ARDB ");
|
||||
+
|
||||
+ /* Initialize i2c early for Serial flash bank information */
|
||||
+ i2c_set_bus_num(0);
|
||||
+
|
||||
+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
|
||||
+ printf("Error reading i2c boot information!\n");
|
||||
+ return 0; /* Don't want to hang() on this error */
|
||||
+ }
|
||||
+
|
||||
+ puts("Version");
|
||||
+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
|
||||
+ puts(": RevA");
|
||||
+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
|
||||
+ puts(": RevB");
|
||||
+ else
|
||||
+ puts(": unknown");
|
||||
+
|
||||
+ printf(", boot from QSPI");
|
||||
+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
|
||||
+ puts(": emu\n");
|
||||
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
|
||||
+ puts(": bank1\n");
|
||||
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
|
||||
+ puts(": bank2\n");
|
||||
+ else
|
||||
+ puts("unknown\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void mmdc_init(void)
|
||||
+{
|
||||
+ struct mmdc_p_regs *mmdc =
|
||||
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
+
|
||||
+ /* Set MMDC_MDSCR[CON_REQ] */
|
||||
+ out_be32(&mmdc->mdscr, 0x00008000);
|
||||
+
|
||||
+ /* configure timing parms */
|
||||
+ out_be32(&mmdc->mdotc, 0x12554000);
|
||||
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
+ out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
+
|
||||
+ /* other parms */
|
||||
+ out_be32(&mmdc->mdmisc, 0x00000680);
|
||||
+ out_be32(&mmdc->mpmur0, 0x00000800);
|
||||
+ out_be32(&mmdc->mdrwd, 0x00002000);
|
||||
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
+
|
||||
+ /* out of reset delays */
|
||||
+ out_be32(&mmdc->mdor, 0x00bf1023);
|
||||
+
|
||||
+ /* physical parms */
|
||||
+ out_be32(&mmdc->mdctl, 0x05180000);
|
||||
+ out_be32(&mmdc->mdasp, 0x0000007f);
|
||||
+
|
||||
+ /* Enable MMDC */
|
||||
+ out_be32(&mmdc->mdctl, 0x85180000);
|
||||
+
|
||||
+ /* dram init sequence: update MRs */
|
||||
+ out_be32(&mmdc->mdscr, 0x00088032);
|
||||
+ out_be32(&mmdc->mdscr, 0x00008033);
|
||||
+ out_be32(&mmdc->mdscr, 0x00048031);
|
||||
+ out_be32(&mmdc->mdscr, 0x19308030);
|
||||
+
|
||||
+ /* dram init sequence: ZQCL */
|
||||
+ out_be32(&mmdc->mdscr, 0x04008040);
|
||||
+ out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ /* Calibrations now: wr lvl */
|
||||
+ out_be32(&mmdc->mdscr, 0x00848031);
|
||||
+ out_be32(&mmdc->mdscr, 0x00008200);
|
||||
+ out_be32(&mmdc->mpwlgcr, 0x00000001);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ out_be32(&mmdc->mdscr, 0x00048031);
|
||||
+ out_be32(&mmdc->mdscr, 0x00008000);
|
||||
+
|
||||
+ /* manual_refresh */
|
||||
+ out_be32(&mmdc->mdscr, 0x00008020);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ /* Calibrations now: Read DQS gating calibration */
|
||||
+ out_be32(&mmdc->mdscr, 0x04008050);
|
||||
+ out_be32(&mmdc->mdscr, 0x00048033);
|
||||
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
+ out_be32(&mmdc->mprddlctl, 0x40404040);
|
||||
+ out_be32(&mmdc->mpdgctrl0, 0x10000000);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ out_be32(&mmdc->mdscr, 0x00008033);
|
||||
+
|
||||
+ /* manual_refresh */
|
||||
+ out_be32(&mmdc->mdscr, 0x00008020);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ /* Calibrations now: Read calibration */
|
||||
+ out_be32(&mmdc->mdscr, 0x04008050);
|
||||
+ out_be32(&mmdc->mdscr, 0x00048033);
|
||||
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
+ out_be32(&mmdc->mprddlhwctl, 0x00000010);
|
||||
+
|
||||
+ mdelay(400);
|
||||
+
|
||||
+ out_be32(&mmdc->mdscr, 0x00008033);
|
||||
+
|
||||
+ /* manual_refresh */
|
||||
+ out_be32(&mmdc->mdscr, 0x00008020);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ /* PD, SR */
|
||||
+ out_be32(&mmdc->mdpdc, 0x00030035);
|
||||
+ out_be32(&mmdc->mapsr, 0x00001067);
|
||||
+
|
||||
+ /* refresh scheme */
|
||||
+ out_be32(&mmdc->mdref, 0x103e8000);
|
||||
+
|
||||
+ mdelay(400);
|
||||
+
|
||||
+ /* disable CON_REQ */
|
||||
+ out_be32(&mmdc->mdscr, 0x0);
|
||||
+
|
||||
+ mdelay(50);
|
||||
+}
|
||||
+
|
||||
+int dram_init(void)
|
||||
+{
|
||||
+ mmdc_init();
|
||||
+
|
||||
+ gd->ram_size = 0x40000000;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int board_eth_init(bd_t *bis)
|
||||
+{
|
||||
+ return pci_eth_init(bis);
|
||||
+}
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ fsl_lsch2_early_init_f();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int board_init(void)
|
||||
+{
|
||||
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
+ /*
|
||||
+ * Set CCI-400 control override register to enable barrier
|
||||
+ * transaction
|
||||
+ */
|
||||
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
||||
+
|
||||
+#ifdef CONFIG_ENV_IS_NOWHERE
|
||||
+ gd->env_addr = (ulong)&default_environment[0];
|
||||
+#endif
|
||||
+
|
||||
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
|
||||
+ enable_layerscape_ns_access();
|
||||
+#endif
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int ft_board_setup(void *blob, bd_t *bd)
|
||||
+{
|
||||
+ u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
+ u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
+
|
||||
+ /* fixup DT for the two DDR banks */
|
||||
+ base[0] = gd->bd->bi_dram[0].start;
|
||||
+ size[0] = gd->bd->bi_dram[0].size;
|
||||
+ base[1] = gd->bd->bi_dram[1].start;
|
||||
+ size[1] = gd->bd->bi_dram[1].size;
|
||||
+
|
||||
+ fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
+ ft_cpu_setup(blob, bd);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
|
||||
new file mode 100644
|
||||
index 0000000..f819038
|
||||
--- /dev/null
|
||||
+++ b/configs/ls1012ardb_qspi_defconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TARGET_LS1012ARDB=y
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
+# CONFIG_CMD_IMLS is not set
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
+CONFIG_OF_CONTROL=y
|
||||
+CONFIG_DM=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_DM_SPI=y
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 9ed04f9..3fd360a 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -12,7 +12,7 @@
|
||||
#define CONFIG_LS1012A
|
||||
#define CONFIG_GICV2
|
||||
|
||||
-#define CONFIG_SYS_HAS_SERDES
|
||||
+#define CONFIG_SYS_HAS_SERDES
|
||||
|
||||
#include <asm/arch/config.h>
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
@@ -56,7 +56,6 @@
|
||||
#define CONFIG_ENV_SPI_MODE 0x03
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
-#define CONFIG_SPI_FLASH_ATMEL
|
||||
#define CONFIG_FSL_SPI_INTERFACE
|
||||
#define CONFIG_SF_DATAFLASH
|
||||
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
new file mode 100644
|
||||
index 0000000..9ff5935
|
||||
--- /dev/null
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -0,0 +1,61 @@
|
||||
+/*
|
||||
+ * Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __LS1012ARDB_H__
|
||||
+#define __LS1012ARDB_H__
|
||||
+
|
||||
+#include "ls1012a_common.h"
|
||||
+
|
||||
+
|
||||
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
+#define CONFIG_NR_DRAM_BANKS 2
|
||||
+
|
||||
+#define CONFIG_CMD_MEMINFO
|
||||
+#define CONFIG_CMD_MEMTEST
|
||||
+#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
+
|
||||
+#define CONFIG_PHYLIB
|
||||
+#define CONFIG_PHY_REALTEK
|
||||
+#define SGMII_PHY1_ADDR 0x0
|
||||
+#define RGMII_PHY2_ADDR 0x1
|
||||
+
|
||||
+/*
|
||||
+* USB
|
||||
+*/
|
||||
+#define CONFIG_HAS_FSL_XHCI_USB
|
||||
+
|
||||
+#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
+#define CONFIG_USB_XHCI
|
||||
+#define CONFIG_USB_XHCI_FSL
|
||||
+#define CONFIG_USB_XHCI_DWC3
|
||||
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
+#define CONFIG_CMD_USB
|
||||
+#define CONFIG_USB_STORAGE
|
||||
+#define CONFIG_CMD_EXT2
|
||||
+#endif
|
||||
+
|
||||
+/*
|
||||
+ * I2C IO expander
|
||||
+ */
|
||||
+
|
||||
+#define I2C_MUX_IO1_ADDR 0x24
|
||||
+#define __SW_BOOT_MASK 0xFC
|
||||
+#define __SW_BOOT_EMU 0x10
|
||||
+#define __SW_BOOT_BANK1 0x00
|
||||
+#define __SW_BOOT_BANK2 0x01
|
||||
+#define __SW_REV_MASK 0x07
|
||||
+#define __SW_REV_A 0xF8
|
||||
+#define __SW_REV_B 0xF0
|
||||
+
|
||||
+#define CONFIG_CMD_MEMINFO
|
||||
+#define CONFIG_CMD_MEMTEST
|
||||
+#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
+
|
||||
+#endif /* __LS1012ARDB_H__ */
|
||||
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
|
||||
index 72a5d5b..7ab88c3 100644
|
||||
--- a/include/linux/usb/xhci-fsl.h
|
||||
+++ b/include/linux/usb/xhci-fsl.h
|
||||
@@ -62,7 +62,7 @@ struct fsl_xhci {
|
||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
-#elif defined(CONFIG_LS1043A)
|
||||
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,80 +0,0 @@ |
||||
From 4aa3d79020aeca3780ea113a495d18662d593761 Mon Sep 17 00:00:00 2001
|
||||
From: Lokesh Vutla <lokeshvutla@ti.com>
|
||||
Date: Thu, 24 Mar 2016 16:02:00 +0530
|
||||
Subject: [PATCH 16/93] ARM: asm: types: Introduce DMA_ADDR_T_64BIT
|
||||
|
||||
dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
|
||||
addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs,
|
||||
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
|
||||
kernel virtual addresses, so they don't care about the size of the actual
|
||||
bus addresses.
|
||||
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
|
||||
DMA still use 32bit address like in case of DRA7 and Keystone platforms.
|
||||
|
||||
This is inspired from the Linux kernel types implementation[1]
|
||||
|
||||
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142
|
||||
|
||||
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
|
||||
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
||||
Reviewed-by: Tom Rini <trini@konsulko.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/Kconfig | 4 ++++
|
||||
arch/arm/include/asm/types.h | 17 +++++++++++++++--
|
||||
2 files changed, 19 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
|
||||
index 5c20801..b536684 100644
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -7,6 +7,10 @@ config SYS_ARCH
|
||||
config ARM64
|
||||
bool
|
||||
|
||||
+config DMA_ADDR_T_64BIT
|
||||
+ bool
|
||||
+ default y if ARM64
|
||||
+
|
||||
config HAS_VBAR
|
||||
bool
|
||||
|
||||
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
|
||||
index 388058e..d108915 100644
|
||||
--- a/arch/arm/include/asm/types.h
|
||||
+++ b/arch/arm/include/asm/types.h
|
||||
@@ -46,16 +46,29 @@ typedef unsigned long long u64;
|
||||
#endif /* CONFIG_ARM64 */
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
-typedef unsigned long long dma_addr_t;
|
||||
typedef unsigned long long phys_addr_t;
|
||||
typedef unsigned long long phys_size_t;
|
||||
#else
|
||||
/* DMA addresses are 32-bits wide */
|
||||
-typedef u32 dma_addr_t;
|
||||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
#endif
|
||||
|
||||
+/*
|
||||
+ * A dma_addr_t can hold any valid DMA address, i.e., any address returned
|
||||
+ * by the DMA API.
|
||||
+ *
|
||||
+ * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
|
||||
+ * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
|
||||
+ * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
|
||||
+ * so they don't care about the size of the actual bus addresses.
|
||||
+ */
|
||||
+#ifdef CONFIG_DMA_ADDR_T_64BIT
|
||||
+typedef unsigned long long dma_addr_t;
|
||||
+#else
|
||||
+typedef u32 dma_addr_t;
|
||||
+#endif
|
||||
+
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
typedef unsigned long resource_size_t;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,465 +0,0 @@ |
||||
From f160c56c71c59d2d865142fdeb3040e9cc4b6a77 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Mon, 25 Apr 2016 17:14:25 +0530
|
||||
Subject: [PATCH 17/93] armv8/fsl-layerscape: add dwc3 gadget driver support
|
||||
|
||||
Implements the dwc3 gadget driver support for LS1043
|
||||
and LS1012 platform.
|
||||
|
||||
NOTE: Do not upstream this patch.It needs rework for open source
|
||||
submission.
|
||||
|
||||
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 98 +++++++++++++++++++-
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++
|
||||
.../include/asm/arch-fsl-layerscape/sys_proto.h | 10 ++
|
||||
common/cmd_usb_mass_storage.c | 2 +-
|
||||
drivers/usb/dwc3/core.c | 12 +++
|
||||
drivers/usb/dwc3/ep0.c | 10 +-
|
||||
drivers/usb/dwc3/gadget.c | 11 ++-
|
||||
drivers/usb/dwc3/io.h | 8 +-
|
||||
drivers/usb/gadget/f_mass_storage.c | 10 +-
|
||||
include/configs/ls1012aqds.h | 15 +++
|
||||
include/configs/ls1012ardb.h | 15 +++
|
||||
include/configs/ls1043aqds.h | 15 +++
|
||||
12 files changed, 197 insertions(+), 15 deletions(-)
|
||||
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
index ec561a7..0a170eb 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
@@ -19,6 +19,10 @@
|
||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||
#include <fsl_validate.h>
|
||||
#endif
|
||||
+#include <usb.h>
|
||||
+#include <dwc3-uboot.h>
|
||||
+#include <linux/usb/xhci-fsl.h>
|
||||
+
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@@ -406,9 +410,19 @@ void fsl_lsch2_early_init_f(void)
|
||||
#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
|
||||
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
|
||||
#endif
|
||||
- /* Make SEC reads and writes snoopable */
|
||||
+
|
||||
+#if defined(CONFIG_LS1043A)
|
||||
+ /* Make SEC and USB reads and writes snoopable */
|
||||
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
|
||||
- SCFG_SNPCNFGCR_SECWRSNP);
|
||||
+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
|
||||
+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
|
||||
+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
|
||||
+ SCFG_SNPCNFGCR_USB3WRSNP);
|
||||
+#elif defined(CONFIG_LS1012A)
|
||||
+ /* Make SEC and reads and writes snoopable */
|
||||
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP |
|
||||
+ SCFG_SNPCNFGCR_USB1RDSNP | SCFG_SNPCNFGCR_USB1WRSNP);
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* Enable snoop requests and DVM message requests for
|
||||
@@ -428,6 +442,86 @@ void fsl_lsch2_early_init_f(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_USB_DWC3
|
||||
+
|
||||
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
+static struct dwc3_device dwc3_device_data0 = {
|
||||
+ .maximum_speed = USB_SPEED_HIGH,
|
||||
+ .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
|
||||
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
|
||||
+ .index = 0,
|
||||
+};
|
||||
+
|
||||
+#if defined(CONFIG_LS1043A)
|
||||
+static struct dwc3_device dwc3_device_data1 = {
|
||||
+ .maximum_speed = USB_SPEED_HIGH,
|
||||
+ .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
|
||||
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
|
||||
+ .index = 1,
|
||||
+};
|
||||
+
|
||||
+static struct dwc3_device dwc3_device_data2 = {
|
||||
+ .maximum_speed = USB_SPEED_HIGH,
|
||||
+ .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
|
||||
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
|
||||
+ .index = 2,
|
||||
+};
|
||||
+#endif
|
||||
+
|
||||
+int usb_gadget_handle_interrupts(int index)
|
||||
+{
|
||||
+ dwc3_uboot_handle_interrupt(index);
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+int board_usb_init(int index, enum usb_init_type init)
|
||||
+{
|
||||
+ switch (init) {
|
||||
+ case USB_INIT_DEVICE:
|
||||
+ switch (index) {
|
||||
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
+ case 0:
|
||||
+ dwc3_uboot_init(&dwc3_device_data0);
|
||||
+ break;
|
||||
+
|
||||
+#if defined(CONFIG_LS1043A)
|
||||
+ case 1:
|
||||
+ dwc3_uboot_init(&dwc3_device_data1);
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ dwc3_uboot_init(&dwc3_device_data2);
|
||||
+ break;
|
||||
+#endif
|
||||
+#endif
|
||||
+ default:
|
||||
+ printf("Invalid Controller Index\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int board_usb_cleanup(int index, enum usb_init_type init)
|
||||
+{
|
||||
+ switch (init) {
|
||||
+ case USB_INIT_DEVICE:
|
||||
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
+ dwc3_uboot_exit(index);
|
||||
+#endif
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+
|
||||
+
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index 5b026f8..414a222 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -355,6 +355,12 @@ struct ccsr_gur {
|
||||
|
||||
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
|
||||
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
|
||||
+#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
|
||||
+#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
|
||||
+#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
|
||||
+#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
|
||||
+#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
|
||||
+#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
|
||||
new file mode 100644
|
||||
index 0000000..1e31d3d
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
|
||||
@@ -0,0 +1,10 @@
|
||||
+/*
|
||||
+ * Copyright 2015 Freescale Semiconductor
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
|
||||
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
|
||||
+
|
||||
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_ */
|
||||
diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
|
||||
index 0407389..7d507b5 100644
|
||||
--- a/common/cmd_usb_mass_storage.c
|
||||
+++ b/common/cmd_usb_mass_storage.c
|
||||
@@ -140,7 +140,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
|
||||
while (1) {
|
||||
usb_gadget_handle_interrupts(controller_index);
|
||||
|
||||
- rc = fsg_main_thread(NULL);
|
||||
+ rc = fsg_main_thread(&controller_index);
|
||||
if (rc) {
|
||||
/* Check I/O error */
|
||||
if (rc == -EIO)
|
||||
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
|
||||
index 85cc96a..b8e4066 100644
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -690,6 +690,18 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
+ /* Change burst beat and outstanding pipelined transfers requests */
|
||||
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
|
||||
+ (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
|
||||
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
|
||||
+ dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
|
||||
+
|
||||
+ /* Enable snooping */
|
||||
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
|
||||
+ dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
|
||||
+#endif
|
||||
+
|
||||
if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
|
||||
dwc->dr_mode = USB_DR_MODE_HOST;
|
||||
else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
|
||||
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
|
||||
index 12b133f..e61d980 100644
|
||||
--- a/drivers/usb/dwc3/ep0.c
|
||||
+++ b/drivers/usb/dwc3/ep0.c
|
||||
@@ -81,8 +81,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
|
||||
trb->ctrl |= (DWC3_TRB_CTRL_IOC
|
||||
| DWC3_TRB_CTRL_LST);
|
||||
|
||||
- dwc3_flush_cache((long)buf_dma, len);
|
||||
- dwc3_flush_cache((long)trb, sizeof(*trb));
|
||||
+ dwc3_flush_cache((uintptr_t)buf_dma, len);
|
||||
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
|
||||
|
||||
if (chain)
|
||||
return 0;
|
||||
@@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
|
||||
if (!r)
|
||||
return;
|
||||
|
||||
- dwc3_flush_cache((long)trb, sizeof(*trb));
|
||||
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
|
||||
|
||||
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
|
||||
if (status == DWC3_TRBSTS_SETUP_PENDING) {
|
||||
@@ -821,7 +821,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
|
||||
ur->actual += transferred;
|
||||
|
||||
trb++;
|
||||
- dwc3_flush_cache((long)trb, sizeof(*trb));
|
||||
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
|
||||
length = trb->size & DWC3_TRB_SIZE_MASK;
|
||||
|
||||
ep0->free_slot = 0;
|
||||
@@ -831,7 +831,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
|
||||
maxp);
|
||||
transferred = min_t(u32, ur->length - transferred,
|
||||
transfer_size - length);
|
||||
- dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
|
||||
+ dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
|
||||
memcpy(buf, dwc->ep0_bounce, transferred);
|
||||
} else {
|
||||
transferred = ur->length - length;
|
||||
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
|
||||
index 8ff949d..649f1a4 100644
|
||||
--- a/drivers/usb/dwc3/gadget.c
|
||||
+++ b/drivers/usb/dwc3/gadget.c
|
||||
@@ -244,7 +244,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
|
||||
|
||||
list_del(&req->list);
|
||||
req->trb = NULL;
|
||||
- dwc3_flush_cache((long)req->request.dma, req->request.length);
|
||||
+ dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
|
||||
|
||||
if (req->request.status == -EINPROGRESS)
|
||||
req->request.status = status;
|
||||
@@ -771,8 +771,8 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
|
||||
|
||||
trb->ctrl |= DWC3_TRB_CTRL_HWO;
|
||||
|
||||
- dwc3_flush_cache((long)dma, length);
|
||||
- dwc3_flush_cache((long)trb, sizeof(*trb));
|
||||
+ dwc3_flush_cache((uintptr_t)dma, length);
|
||||
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1769,7 +1769,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
|
||||
slot %= DWC3_TRB_NUM;
|
||||
trb = &dep->trb_pool[slot];
|
||||
|
||||
- dwc3_flush_cache((long)trb, sizeof(*trb));
|
||||
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
|
||||
__dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
|
||||
dwc3_gadget_giveback(dep, req, status);
|
||||
|
||||
@@ -2447,6 +2447,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
|
||||
int left;
|
||||
u32 reg;
|
||||
|
||||
+
|
||||
evt = dwc->ev_buffs[buf];
|
||||
left = evt->count;
|
||||
|
||||
@@ -2670,7 +2671,7 @@ void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
|
||||
|
||||
for (i = 0; i < dwc->num_event_buffers; i++) {
|
||||
evt = dwc->ev_buffs[i];
|
||||
- dwc3_flush_cache((long)evt->buf, evt->length);
|
||||
+ dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
|
||||
}
|
||||
|
||||
dwc3_thread_interrupt(0, dwc);
|
||||
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
|
||||
index 0d9fa22..cab5122 100644
|
||||
--- a/drivers/usb/dwc3/io.h
|
||||
+++ b/drivers/usb/dwc3/io.h
|
||||
@@ -48,8 +48,14 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
|
||||
writel(value, base + offs);
|
||||
}
|
||||
|
||||
-static inline void dwc3_flush_cache(int addr, int length)
|
||||
+static inline void dwc3_flush_cache(uintptr_t addr, int length)
|
||||
{
|
||||
flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
|
||||
}
|
||||
+
|
||||
+static inline void dwc3_inval_cache(uintptr_t addr, int length)
|
||||
+{
|
||||
+ invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
|
||||
+}
|
||||
+
|
||||
#endif /* __DRIVERS_USB_DWC3_IO_H */
|
||||
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
|
||||
index ec1f23a..ec0229f 100644
|
||||
--- a/drivers/usb/gadget/f_mass_storage.c
|
||||
+++ b/drivers/usb/gadget/f_mass_storage.c
|
||||
@@ -362,6 +362,7 @@ struct fsg_common {
|
||||
char inquiry_string[8 + 16 + 4 + 1];
|
||||
|
||||
struct kref ref;
|
||||
+ unsigned int controller_index;
|
||||
};
|
||||
|
||||
struct fsg_config {
|
||||
@@ -690,7 +691,7 @@ static int sleep_thread(struct fsg_common *common)
|
||||
k = 0;
|
||||
}
|
||||
|
||||
- usb_gadget_handle_interrupts(0);
|
||||
+ usb_gadget_handle_interrupts(common->controller_index);
|
||||
}
|
||||
common->thread_wakeup_needed = 0;
|
||||
return rc;
|
||||
@@ -2405,6 +2406,11 @@ int fsg_main_thread(void *common_)
|
||||
{
|
||||
int ret;
|
||||
struct fsg_common *common = the_fsg_common;
|
||||
+
|
||||
+ /* update the controller_index */
|
||||
+ if (common_)
|
||||
+ common->controller_index = *(unsigned int *)common_;
|
||||
+
|
||||
/* The main loop */
|
||||
do {
|
||||
if (exception_in_progress(common)) {
|
||||
@@ -2475,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
|
||||
|
||||
common->ops = NULL;
|
||||
common->private_data = NULL;
|
||||
+ common->controller_index = 0;
|
||||
|
||||
common->gadget = gadget;
|
||||
common->ep0 = gadget->ep0;
|
||||
@@ -2769,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
|
||||
|
||||
fsg_common->ops = NULL;
|
||||
fsg_common->private_data = NULL;
|
||||
+ fsg_common->controller_index = 0;
|
||||
|
||||
the_fsg_common = fsg_common;
|
||||
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index 6346d3e..fdada18 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -123,6 +123,21 @@
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_EXT2
|
||||
+
|
||||
+#define CONFIG_USB_DWC3
|
||||
+#define CONFIG_USB_DWC3_GADGET
|
||||
+
|
||||
+#define CONFIG_USB_GADGET
|
||||
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
+#define CONFIG_USB_GADGET_DOWNLOAD
|
||||
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
||||
+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
|
||||
+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
|
||||
+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
|
||||
+#define CONFIG_USB_GADGET_DUALSPEED
|
||||
+
|
||||
+/* USB Gadget ums command */
|
||||
+#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index 9ff5935..af3d33f 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -38,6 +38,21 @@
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_EXT2
|
||||
+
|
||||
+#define CONFIG_USB_DWC3
|
||||
+#define CONFIG_USB_DWC3_GADGET
|
||||
+
|
||||
+#define CONFIG_USB_GADGET
|
||||
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
+#define CONFIG_USB_GADGET_DOWNLOAD
|
||||
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
||||
+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
|
||||
+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
|
||||
+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
|
||||
+#define CONFIG_USB_GADGET_DUALSPEED
|
||||
+
|
||||
+/* USB Gadget ums command */
|
||||
+#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
#endif
|
||||
|
||||
/*
|
||||
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
|
||||
index 9828360..9e23615 100644
|
||||
--- a/include/configs/ls1043aqds.h
|
||||
+++ b/include/configs/ls1043aqds.h
|
||||
@@ -400,6 +400,21 @@ unsigned long get_board_ddr_clk(void);
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_EXT2
|
||||
+
|
||||
+#define CONFIG_USB_DWC3
|
||||
+#define CONFIG_USB_DWC3_GADGET
|
||||
+
|
||||
+#define CONFIG_USB_GADGET
|
||||
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
+#define CONFIG_USB_GADGET_DOWNLOAD
|
||||
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
||||
+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
|
||||
+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
|
||||
+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
|
||||
+#define CONFIG_USB_GADGET_DUALSPEED
|
||||
+
|
||||
+/* USB Gadget ums command */
|
||||
+#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
#endif
|
||||
|
||||
/*
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,62 +0,0 @@ |
||||
From 035a4db85bbf28ba1452c49c9f8d05a085f2544b Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Tue, 26 Apr 2016 17:40:05 +0530
|
||||
Subject: [PATCH 18/93] boards: ls1012aqds: Enable SDHC_CD in brdcfg10 of FPGA
|
||||
|
||||
Default configuration of brdcfg10 in FPGA does not enable SDHC_CD
|
||||
signal.
|
||||
|
||||
Enable SDHC_CD by default during boot sequence.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 12 ++++++++++++
|
||||
include/configs/ls1012aqds.h | 3 +++
|
||||
2 files changed, 15 insertions(+)
|
||||
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index ffcd0d8..6d5fef8 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -154,6 +154,18 @@ int board_early_init_f(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_MISC_INIT_R
|
||||
+int misc_init_r(void)
|
||||
+{
|
||||
+ u8 mux_sdhc_cd = 0x80;
|
||||
+
|
||||
+ i2c_set_bus_num(0);
|
||||
+
|
||||
+ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index fdada18..bb433de 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -27,6 +27,7 @@
|
||||
#endif
|
||||
|
||||
#define CONFIG_QIXIS_I2C_ACCESS
|
||||
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
|
||||
/*
|
||||
* I2C bus multiplexer
|
||||
@@ -145,4 +146,6 @@
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
+#define CONFIG_MISC_INIT_R
|
||||
+
|
||||
#endif /* __LS1012AQDS_H__ */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,50 +0,0 @@ |
||||
From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
|
||||
From: Makarand Pawagi <makarand.pawagi@mindspeed.com>
|
||||
Date: Mon, 2 May 2016 09:33:45 +0530
|
||||
Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
|
||||
SAI2, SAI3, SAI4
|
||||
|
||||
Access settings for different IPs has to be enabled through CSU registers. Following
|
||||
IP's are added for LS1012A:
|
||||
Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
|
||||
Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
|
||||
Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
|
||||
Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
|
||||
Added CSU ID for SAI-4, reg: CSL42_REG[23:16
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/ns_access.h | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
index a3ccdb0..d6642a7 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
@@ -69,7 +69,12 @@ enum csu_cslx_ind {
|
||||
CSU_CSLX_IIC4 = 77,
|
||||
CSU_CSLX_WDT4,
|
||||
CSU_CSLX_WDT3,
|
||||
+ CSU_CSLX_ESDHC2 = 80,
|
||||
CSU_CSLX_WDT5 = 81,
|
||||
+ CSU_CSLX_SAI2,
|
||||
+ CSU_CSLX_SAI1,
|
||||
+ CSU_CSLX_SAI4,
|
||||
+ CSU_CSLX_SAI3,
|
||||
CSU_CSLX_FTM2 = 86,
|
||||
CSU_CSLX_FTM1,
|
||||
CSU_CSLX_FTM4,
|
||||
@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
|
||||
{CSU_CSLX_IIC4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT3, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT5, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_SAI2, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_SAI1, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_SAI4, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_SAI3, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM2, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM1, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM4, CSU_ALL_RW},
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,280 +0,0 @@ |
||||
From e8703a5bba4bc0e9fa6aefe0eae7caf9141b8bdc Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Mon, 2 May 2016 18:28:16 +0530
|
||||
Subject: [PATCH 20/93] armv8: ls1012a: Update DDR init sequence
|
||||
|
||||
Current DDR init code uses lots of delay.
|
||||
|
||||
Use wait for bit clear instead of delays.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 67 +++++++++++++++++--------------
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 54 +++++++++++--------------
|
||||
2 files changed, 60 insertions(+), 61 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index 6d5fef8..5cb225f 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -28,6 +28,20 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
|
||||
+{
|
||||
+ int timeout = 1000;
|
||||
+
|
||||
+ out_be32(ptr, value);
|
||||
+
|
||||
+ while (in_be32(ptr) & bits) {
|
||||
+ udelay(100);
|
||||
+ timeout--;
|
||||
+ }
|
||||
+ if (timeout <= 0)
|
||||
+ puts("Error: wait for clear timeout.\n");
|
||||
+}
|
||||
+
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: LS1012AQDS\n");
|
||||
@@ -44,7 +58,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mdscr, 0x00008000);
|
||||
|
||||
/* configure timing parms */
|
||||
- out_be32(&mmdc->mdotc, 0x12554000);
|
||||
+ out_be32(&mmdc->mdotc, 0x12554000);
|
||||
out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
@@ -56,7 +70,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
|
||||
/* out of reset delays */
|
||||
- out_be32(&mmdc->mdor, 0x00bf1023);
|
||||
+ out_be32(&mmdc->mdor, 0x00bf1023);
|
||||
|
||||
/* physical parms */
|
||||
out_be32(&mmdc->mdctl, 0x05180000);
|
||||
@@ -73,69 +87,60 @@ void mmdc_init(void)
|
||||
|
||||
/* dram init sequence: ZQCL */
|
||||
out_be32(&mmdc->mdscr, 0x04008040);
|
||||
- out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
|
||||
-
|
||||
- mdelay(100);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
|
||||
|
||||
/* Calibrations now: wr lvl */
|
||||
out_be32(&mmdc->mdscr, 0x00848031);
|
||||
out_be32(&mmdc->mdscr, 0x00008200);
|
||||
- out_be32(&mmdc->mpwlgcr, 0x00000001);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
|
||||
|
||||
- mdelay(100);
|
||||
+ mdelay(1);
|
||||
|
||||
out_be32(&mmdc->mdscr, 0x00048031);
|
||||
out_be32(&mmdc->mdscr, 0x00008000);
|
||||
|
||||
- /* manual_refresh */
|
||||
- out_be32(&mmdc->mdscr, 0x00008020);
|
||||
-
|
||||
- mdelay(100);
|
||||
+ mdelay(1);
|
||||
|
||||
/* Calibrations now: Read DQS gating calibration */
|
||||
out_be32(&mmdc->mdscr, 0x04008050);
|
||||
out_be32(&mmdc->mdscr, 0x00048033);
|
||||
out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
out_be32(&mmdc->mprddlctl, 0x40404040);
|
||||
- out_be32(&mmdc->mpdgctrl0, 0x10000000);
|
||||
-
|
||||
- mdelay(100);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
|
||||
|
||||
out_be32(&mmdc->mdscr, 0x00008033);
|
||||
|
||||
- /* manual_refresh */
|
||||
- out_be32(&mmdc->mdscr, 0x00008020);
|
||||
-
|
||||
- mdelay(100);
|
||||
|
||||
/* Calibrations now: Read calibration */
|
||||
out_be32(&mmdc->mdscr, 0x04008050);
|
||||
out_be32(&mmdc->mdscr, 0x00048033);
|
||||
out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
- out_be32(&mmdc->mprddlhwctl, 0x00000010);
|
||||
-
|
||||
- mdelay(400);
|
||||
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
|
||||
|
||||
out_be32(&mmdc->mdscr, 0x00008033);
|
||||
|
||||
- /* manual_refresh */
|
||||
- out_be32(&mmdc->mdscr, 0x00008020);
|
||||
-
|
||||
- mdelay(100);
|
||||
-
|
||||
/* PD, SR */
|
||||
out_be32(&mmdc->mdpdc, 0x00030035);
|
||||
out_be32(&mmdc->mapsr, 0x00001067);
|
||||
|
||||
/* refresh scheme */
|
||||
- out_be32(&mmdc->mdref, 0x103e8000);
|
||||
-
|
||||
- mdelay(400);
|
||||
+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
|
||||
|
||||
/* disable CON_REQ */
|
||||
out_be32(&mmdc->mdscr, 0x0);
|
||||
+}
|
||||
|
||||
- mdelay(50);
|
||||
+int select_i2c_ch_pca9547(u8 ch)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
|
||||
+ if (ret) {
|
||||
+ puts("PCA: failed to select proper channel\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
@@ -183,6 +188,8 @@ int board_init(void)
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE
|
||||
gd->env_addr = (ulong)&default_environment[0];
|
||||
#endif
|
||||
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index 4a7aaaa..f7b9bce 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -23,6 +23,20 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
|
||||
+{
|
||||
+ int timeout = 1000;
|
||||
+
|
||||
+ out_be32(ptr, value);
|
||||
+
|
||||
+ while (in_be32(ptr) & bits) {
|
||||
+ udelay(100);
|
||||
+ timeout--;
|
||||
+ }
|
||||
+ if (timeout <= 0)
|
||||
+ puts("Error: wait for clear timeout.\n");
|
||||
+}
|
||||
+
|
||||
int checkboard(void)
|
||||
{
|
||||
u8 in1;
|
||||
@@ -67,7 +81,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mdscr, 0x00008000);
|
||||
|
||||
/* configure timing parms */
|
||||
- out_be32(&mmdc->mdotc, 0x12554000);
|
||||
+ out_be32(&mmdc->mdotc, 0x12554000);
|
||||
out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
@@ -79,7 +93,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
|
||||
/* out of reset delays */
|
||||
- out_be32(&mmdc->mdor, 0x00bf1023);
|
||||
+ out_be32(&mmdc->mdor, 0x00bf1023);
|
||||
|
||||
/* physical parms */
|
||||
out_be32(&mmdc->mdctl, 0x05180000);
|
||||
@@ -96,69 +110,47 @@ void mmdc_init(void)
|
||||
|
||||
/* dram init sequence: ZQCL */
|
||||
out_be32(&mmdc->mdscr, 0x04008040);
|
||||
- out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
|
||||
-
|
||||
- mdelay(100);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
|
||||
|
||||
/* Calibrations now: wr lvl */
|
||||
out_be32(&mmdc->mdscr, 0x00848031);
|
||||
out_be32(&mmdc->mdscr, 0x00008200);
|
||||
- out_be32(&mmdc->mpwlgcr, 0x00000001);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
|
||||
|
||||
- mdelay(100);
|
||||
+ mdelay(1);
|
||||
|
||||
out_be32(&mmdc->mdscr, 0x00048031);
|
||||
out_be32(&mmdc->mdscr, 0x00008000);
|
||||
|
||||
- /* manual_refresh */
|
||||
- out_be32(&mmdc->mdscr, 0x00008020);
|
||||
-
|
||||
- mdelay(100);
|
||||
+ mdelay(1);
|
||||
|
||||
/* Calibrations now: Read DQS gating calibration */
|
||||
out_be32(&mmdc->mdscr, 0x04008050);
|
||||
out_be32(&mmdc->mdscr, 0x00048033);
|
||||
out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
out_be32(&mmdc->mprddlctl, 0x40404040);
|
||||
- out_be32(&mmdc->mpdgctrl0, 0x10000000);
|
||||
-
|
||||
- mdelay(100);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
|
||||
|
||||
out_be32(&mmdc->mdscr, 0x00008033);
|
||||
|
||||
- /* manual_refresh */
|
||||
- out_be32(&mmdc->mdscr, 0x00008020);
|
||||
-
|
||||
- mdelay(100);
|
||||
|
||||
/* Calibrations now: Read calibration */
|
||||
out_be32(&mmdc->mdscr, 0x04008050);
|
||||
out_be32(&mmdc->mdscr, 0x00048033);
|
||||
out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
- out_be32(&mmdc->mprddlhwctl, 0x00000010);
|
||||
-
|
||||
- mdelay(400);
|
||||
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
|
||||
|
||||
out_be32(&mmdc->mdscr, 0x00008033);
|
||||
|
||||
- /* manual_refresh */
|
||||
- out_be32(&mmdc->mdscr, 0x00008020);
|
||||
-
|
||||
- mdelay(100);
|
||||
-
|
||||
/* PD, SR */
|
||||
out_be32(&mmdc->mdpdc, 0x00030035);
|
||||
out_be32(&mmdc->mapsr, 0x00001067);
|
||||
|
||||
/* refresh scheme */
|
||||
- out_be32(&mmdc->mdref, 0x103e8000);
|
||||
-
|
||||
- mdelay(400);
|
||||
+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
|
||||
|
||||
/* disable CON_REQ */
|
||||
out_be32(&mmdc->mdscr, 0x0);
|
||||
-
|
||||
- mdelay(50);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,26 +0,0 @@ |
||||
From 90ded6778736d5a0843d24eb8e5a47db72c05af9 Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Mon, 18 Apr 2016 22:44:21 +0800
|
||||
Subject: [PATCH 21/93] sf: set the Uniform Sector to CR3NV instead of CR3V
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index 865e929..97e53c7 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -942,7 +942,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
|
||||
static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
|
||||
{
|
||||
u8 cmd[4];
|
||||
- u32 offset = 0x800004; /* CR3V register offset */
|
||||
+ u32 offset = 0x000004; /* CR3NV register offset */
|
||||
u8 cr3v;
|
||||
int ret;
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,124 +0,0 @@ |
||||
From 46c9963880e5cba6390864477f19b25369c6c944 Mon Sep 17 00:00:00 2001
|
||||
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Date: Thu, 5 May 2016 15:01:02 +0530
|
||||
Subject: [PATCH 22/93] include: usb: Rename USB controller base address
|
||||
mapping
|
||||
|
||||
[context adjustment]
|
||||
|
||||
Remove Soc specific defines and use generic chasis specific defines
|
||||
for USB controller base address mapping.
|
||||
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 +++---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++--
|
||||
arch/arm/include/asm/arch-ls102xa/config.h | 6 ++----
|
||||
include/linux/usb/xhci-fsl.h | 20 ++++++++------------
|
||||
include/usb/ehci-fsl.h | 2 +-
|
||||
5 files changed, 16 insertions(+), 22 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index 414a222..3e37f00 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -33,9 +33,9 @@
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
|
||||
-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
|
||||
-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
|
||||
-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
|
||||
+#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
|
||||
+#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
||||
index 0ab709c..cf1f37a 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
||||
@@ -51,8 +51,8 @@
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
|
||||
-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
+#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
|
||||
index 926ac58..05fff80 100644
|
||||
--- a/arch/arm/include/asm/arch-ls102xa/config.h
|
||||
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
|
||||
@@ -36,13 +36,11 @@
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
|
||||
-#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
-#define CONFIG_SYS_LS102XA_USB1_ADDR \
|
||||
- (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
|
||||
+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
+#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
|
||||
-#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
|
||||
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
|
||||
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
|
||||
index 7ab88c3..b2b3264 100644
|
||||
--- a/include/linux/usb/xhci-fsl.h
|
||||
+++ b/include/linux/usb/xhci-fsl.h
|
||||
@@ -54,22 +54,18 @@ struct fsl_xhci {
|
||||
struct dwc3 *dwc3_reg;
|
||||
};
|
||||
|
||||
-#if defined(CONFIG_LS102XA)
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
|
||||
+#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
-#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
|
||||
-#elif defined(CONFIG_LS1012A)
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
|
||||
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
+#elif defined(CONFIG_LS1043A)
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
|
||||
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
|
||||
#endif
|
||||
|
||||
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
|
||||
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
|
||||
index e9349b5..b8d78d0 100644
|
||||
--- a/include/usb/ehci-fsl.h
|
||||
+++ b/include/usb/ehci-fsl.h
|
||||
@@ -164,7 +164,7 @@
|
||||
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_USB2_ADDR 0
|
||||
#elif defined(CONFIG_LS102XA)
|
||||
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
|
||||
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_USB2_ADDR 0
|
||||
#endif
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,65 +0,0 @@ |
||||
From 271adb5c0546b080fb350a41520c600a16739f1a Mon Sep 17 00:00:00 2001
|
||||
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Date: Fri, 6 May 2016 09:05:29 +0530
|
||||
Subject: [PATCH 23/93] drivers: usb: fsl: add USB ULPI init code
|
||||
|
||||
This adds the required code to set up a ULPI USB port, for
|
||||
new NXP USB PHY used in QorIQ platforms.
|
||||
|
||||
To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
|
||||
have to be set in the board configuration file.
|
||||
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
---
|
||||
drivers/usb/host/ehci-fsl.c | 21 +++++++++++++++++++++
|
||||
1 file changed, 21 insertions(+)
|
||||
|
||||
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
|
||||
index 97b7f14..3f06345 100644
|
||||
--- a/drivers/usb/host/ehci-fsl.c
|
||||
+++ b/drivers/usb/host/ehci-fsl.c
|
||||
@@ -16,6 +16,9 @@
|
||||
#include <hwconfig.h>
|
||||
#include <fsl_usb.h>
|
||||
#include <fdt_support.h>
|
||||
+#ifdef CONFIG_USB_ULPI
|
||||
+#include <usb/ulpi.h>
|
||||
+#endif
|
||||
|
||||
#include "ehci.h"
|
||||
|
||||
@@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
||||
const char *phy_type = NULL;
|
||||
size_t len;
|
||||
char current_usb_controller[5];
|
||||
+#ifdef CONFIG_USB_ULPI
|
||||
+ int ret;
|
||||
+ struct ulpi_viewport ulpi_vp;
|
||||
+#endif
|
||||
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
char usb_phy[5];
|
||||
|
||||
@@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
||||
udelay(1000); /* delay required for PHY Clk to appear */
|
||||
if (!usb_phy_clk_valid(ehci))
|
||||
return -EINVAL;
|
||||
+
|
||||
+#ifdef CONFIG_USB_ULPI
|
||||
+ ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
|
||||
+ ulpi_vp.port_num = 0;
|
||||
+
|
||||
+ ret = ulpi_init(&ulpi_vp);
|
||||
+ if (ret) {
|
||||
+ puts("NXP ULPI viewport init failed\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ ulpi_set_vbus(&ulpi_vp, 1, 1);
|
||||
+ ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 1);
|
||||
+#endif
|
||||
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
|
||||
}
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,67 +0,0 @@ |
||||
From dec7ec15a9c2f2c3e0a09bb9cda8a24e4d469242 Mon Sep 17 00:00:00 2001
|
||||
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Date: Fri, 6 May 2016 09:09:32 +0530
|
||||
Subject: [PATCH 24/93] config: ls1012aqds: Add USB EHCI support for
|
||||
ls1012aqds
|
||||
|
||||
Add USB EHCI support for ls1012aqds platform
|
||||
|
||||
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
|
||||
include/configs/ls1012aqds.h | 5 +++++
|
||||
include/usb/ehci-fsl.h | 2 +-
|
||||
3 files changed, 7 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index 3e37f00..24add1a 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -36,6 +36,7 @@
|
||||
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
|
||||
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
|
||||
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
+#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index bb433de..51ca902 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -109,6 +109,8 @@
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
+#define CONFIG_USB_ULPI
|
||||
+#define CONFIG_USB_ULPI_VIEWPORT
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#endif
|
||||
|
||||
@@ -121,6 +123,9 @@
|
||||
#define CONFIG_USB_XHCI_DWC3
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
+#endif
|
||||
+
|
||||
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_EXT2
|
||||
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
|
||||
index b8d78d0..94b1efa 100644
|
||||
--- a/include/usb/ehci-fsl.h
|
||||
+++ b/include/usb/ehci-fsl.h
|
||||
@@ -163,7 +163,7 @@
|
||||
#elif defined(CONFIG_MPC512X)
|
||||
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_USB2_ADDR 0
|
||||
-#elif defined(CONFIG_LS102XA)
|
||||
+#elif defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
|
||||
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_USB2_ADDR 0
|
||||
#endif
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,115 +0,0 @@ |
||||
From 93a1095c7da7291ffb12116de9122d431b9f6113 Mon Sep 17 00:00:00 2001
|
||||
From: Sumit Garg <sumit.garg@nxp.com>
|
||||
Date: Fri, 6 May 2016 11:11:58 -0400
|
||||
Subject: [PATCH 25/93] armv8: ls1012ardb: Add qspi SECURE BOOT target
|
||||
|
||||
Add qspi SECURE BOOT target to enable chain of trust. Also enable
|
||||
sec_init in boot sequence.
|
||||
|
||||
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
|
||||
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 +++++++
|
||||
arch/arm/include/asm/fsl_secure_boot.h | 7 ++++++-
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 5 +++++
|
||||
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 10 ++++++++++
|
||||
include/configs/ls1012ardb.h | 2 ++
|
||||
5 files changed, 30 insertions(+), 1 deletion(-)
|
||||
create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
index 6ea4e8e..679be6c 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
@@ -237,6 +237,13 @@
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009798
|
||||
|
||||
+#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
+#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
+#define CONFIG_SYS_FSL_SEC_BE
|
||||
+#define CONFIG_SYS_FSL_SFP_BE
|
||||
+#define CONFIG_SYS_FSL_SRK_LE
|
||||
+#define CONFIG_KEY_REVOCATION
|
||||
+
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
|
||||
index c7f8b3e..c973255 100644
|
||||
--- a/arch/arm/include/asm/fsl_secure_boot.h
|
||||
+++ b/arch/arm/include/asm/fsl_secure_boot.h
|
||||
@@ -50,7 +50,7 @@
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
|
||||
- defined(CONFIG_LS2085A)
|
||||
+ defined(CONFIG_LS2085A) || defined(CONFIG_LS1012A)
|
||||
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
|
||||
* Similiarly for LS2080 and LS2085
|
||||
*/
|
||||
@@ -81,6 +81,11 @@
|
||||
#define CONFIG_BS_ADDR_FLASH 0x583900000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
|
||||
#define CONFIG_BS_ADDR_RAM 0xa3900000
|
||||
+#elif defined(CONFIG_LS1012A)
|
||||
+#define CONFIG_BS_HDR_ADDR_FLASH 0x400c0000
|
||||
+#define CONFIG_BS_ADDR_FLASH 0x40060000
|
||||
+#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
|
||||
+#define CONFIG_BS_ADDR_RAM 0xa0060000
|
||||
#else
|
||||
#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
|
||||
#define CONFIG_BS_ADDR_FLASH 0x60060000
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index f7b9bce..347b8c8 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -20,6 +20,7 @@
|
||||
#include <environment.h>
|
||||
#include <fsl_mmdc.h>
|
||||
#include <netdev.h>
|
||||
+#include <fsl_sec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@@ -191,6 +192,10 @@ int board_init(void)
|
||||
enable_layerscape_ns_access();
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_FSL_CAAM
|
||||
+ sec_init();
|
||||
+#endif
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
new file mode 100644
|
||||
index 0000000..92a95a8
|
||||
--- /dev/null
|
||||
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TARGET_LS1012ARDB=y
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
|
||||
+# CONFIG_CMD_IMLS is not set
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
+CONFIG_OF_CONTROL=y
|
||||
+CONFIG_DM=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_DM_SPI=y
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index af3d33f..b40e02b 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -73,4 +73,6 @@
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
+#define CONFIG_FSL_CAAM /* Enable CAAM */
|
||||
+
|
||||
#endif /* __LS1012ARDB_H__ */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,38 +0,0 @@ |
||||
From d99349711fa42b3e401bf9a71e315440b8ed2c17 Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Tue, 10 May 2016 09:21:35 +0530
|
||||
Subject: [PATCH 26/93] fsl, qixis: conditionally compile IFC based qixis
|
||||
functions
|
||||
|
||||
Check if qixis supports memory-mapped read/write
|
||||
before compiling IFC based qixis read/write functions.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
board/freescale/common/qixis.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
|
||||
index 113295f..2e35d41 100644
|
||||
--- a/board/freescale/common/qixis.c
|
||||
+++ b/board/freescale/common/qixis.c
|
||||
@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
|
||||
}
|
||||
#endif
|
||||
|
||||
+#ifdef QIXIS_BASE
|
||||
u8 qixis_read(unsigned int reg)
|
||||
{
|
||||
void *p = (void *)QIXIS_BASE;
|
||||
@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
|
||||
|
||||
out_8(p + reg, value);
|
||||
}
|
||||
+#endif
|
||||
|
||||
u16 qixis_read_minor(void)
|
||||
{
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,48 +0,0 @@ |
||||
From 34a472a20695cbd6ab1bc2d0686c6f324d8e0d6c Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Tue, 10 May 2016 09:38:46 +0530
|
||||
Subject: [PATCH 27/93] fsl, qixis: Add flag for LBMAP brdcfg reg offset
|
||||
|
||||
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
|
||||
configuration register instead of hardcoding it in
|
||||
set_lbmap() function.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
board/freescale/common/qixis.c | 11 +++++++++--
|
||||
1 file changed, 9 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
|
||||
index 2e35d41..0db0ed6 100644
|
||||
--- a/board/freescale/common/qixis.c
|
||||
+++ b/board/freescale/common/qixis.c
|
||||
@@ -14,6 +14,13 @@
|
||||
#include <i2c.h>
|
||||
#include "qixis.h"
|
||||
|
||||
+#ifndef QIXIS_LBMAP_BRDCFG_REG
|
||||
+/*
|
||||
+ * For consistency with existing platforms
|
||||
+ */
|
||||
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
|
||||
u8 qixis_read_i2c(unsigned int reg)
|
||||
{
|
||||
@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
|
||||
{
|
||||
u8 reg;
|
||||
|
||||
- reg = QIXIS_READ(brdcfg[0]);
|
||||
+ reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
|
||||
reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
|
||||
- QIXIS_WRITE(brdcfg[0], reg);
|
||||
+ QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
|
||||
}
|
||||
|
||||
static void __maybe_unused set_rcw_src(int rcw_src)
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,80 +0,0 @@ |
||||
From 4fcb1d5141ff6d9527ceac9f391e1da4128f5a60 Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Tue, 10 May 2016 09:54:36 +0530
|
||||
Subject: [PATCH 28/93] fsl, ls1012a, qixis: Add support for qixis subsystem
|
||||
|
||||
Add support for the printing FPGA build information,
|
||||
altbank switching and board reset using qixis subsystem.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 20 +++++++++++++++++++-
|
||||
include/configs/ls1012aqds.h | 17 +++++++++++++++++
|
||||
2 files changed, 36 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index 5cb225f..446989b 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -44,8 +44,26 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
- puts("Board: LS1012AQDS\n");
|
||||
+ char buf[64];
|
||||
+ u8 sw;
|
||||
|
||||
+ sw = QIXIS_READ(arch);
|
||||
+ printf("Board Arch: V%d, ", sw >> 4);
|
||||
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
|
||||
+
|
||||
+ sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
|
||||
+
|
||||
+ if (sw & QIXIS_LBMAP_ALTBANK)
|
||||
+ printf("flash: 2\n");
|
||||
+ else
|
||||
+ printf("flash: 1\n");
|
||||
+
|
||||
+ printf("FPGA: v%d (%s), build %d",
|
||||
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
|
||||
+ (int)qixis_read_minor());
|
||||
+
|
||||
+ /* the timestamp string contains "\n" at the end */
|
||||
+ printf(" on %s", qixis_read_time(buf));
|
||||
return 0;
|
||||
}
|
||||
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index 51ca902..de998b8 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -26,8 +26,25 @@
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||
#endif
|
||||
|
||||
+/*
|
||||
+ * QIXIS Definitions
|
||||
+ */
|
||||
+#define CONFIG_FSL_QIXIS
|
||||
+
|
||||
+#ifdef CONFIG_FSL_QIXIS
|
||||
#define CONFIG_QIXIS_I2C_ACCESS
|
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
+#define QIXIS_LBMAP_BRDCFG_REG 0x04
|
||||
+#define QIXIS_LBMAP_SWITCH 6
|
||||
+#define QIXIS_LBMAP_MASK 0xf7
|
||||
+#define QIXIS_LBMAP_SHIFT 0
|
||||
+#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
+#define QIXIS_LBMAP_ALTBANK 0x08
|
||||
+#define QIXIS_RST_CTL_RESET 0x41
|
||||
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* I2C bus multiplexer
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,37 +0,0 @@ |
||||
From 57700b94f9111578d0fc05bb8f273c0b29951572 Mon Sep 17 00:00:00 2001
|
||||
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Date: Wed, 11 May 2016 14:59:39 +0530
|
||||
Subject: [PATCH 29/93] armv8: ls1012a: Added CSU assignment for USB2
|
||||
|
||||
Access settings for USB2 IP is added through CSU register.
|
||||
|
||||
Added CSU ID for USB2, reg: CSL23_REG[8:0]
|
||||
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
index d6642a7..2fd33e1 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
@@ -38,6 +38,7 @@ enum csu_cslx_ind {
|
||||
CSU_CSLX_ESDHC,
|
||||
CSU_CSLX_IFC = 45,
|
||||
CSU_CSLX_I2C1,
|
||||
+ CSU_CSLX_USB_2,
|
||||
CSU_CSLX_I2C3 = 48,
|
||||
CSU_CSLX_I2C2,
|
||||
CSU_CSLX_DUART2 = 50,
|
||||
@@ -117,6 +118,7 @@ static struct csu_ns_dev ns_dev[] = {
|
||||
{CSU_CSLX_ESDHC, CSU_ALL_RW},
|
||||
{CSU_CSLX_IFC, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C1, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_USB_2, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C3, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART2, CSU_ALL_RW},
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,32 +0,0 @@ |
||||
From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001
|
||||
From: Sumit Garg <sumit.garg@nxp.com>
|
||||
Date: Wed, 11 May 2016 12:44:35 -0400
|
||||
Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency
|
||||
|
||||
Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
|
||||
The SMPEN bit should be set before enabling the data cache. If not
|
||||
enabled, the cache is not coherent with other cores and data
|
||||
corruption could occur. It also enables core level cache snooping.
|
||||
|
||||
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/start.S | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
|
||||
index 235213f..9703f6b 100644
|
||||
--- a/arch/arm/cpu/armv8/start.S
|
||||
+++ b/arch/arm/cpu/armv8/start.S
|
||||
@@ -70,6 +70,9 @@ reset:
|
||||
mov x0, #3 << 20
|
||||
msr cpacr_el1, x0 /* Enable FP/SIMD */
|
||||
0:
|
||||
+ /* Enalbe SMPEN bit */
|
||||
+ mov x0, #0x40
|
||||
+ msr s3_1_c15_c2_1, x0
|
||||
|
||||
/* Apply ARM core specific erratas */
|
||||
bl apply_core_errata
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,308 +0,0 @@ |
||||
From 6cfe5c5e7f6a4b3d46f65967fe10820ee2e3d2fa Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Fri, 13 May 2016 16:30:33 +0800
|
||||
Subject: [PATCH 31/93] mtd: sf: add exceed flash 16MB support for qspi
|
||||
|
||||
spi/spi_flash.c: The flash S25FS512S cannot legacy commands
|
||||
such as Bank Address Related Command, So we need add the exceed
|
||||
16MB suuport. So we extend the cmd[] size to support 32-bit address,
|
||||
what's more, as to spi/fsl_qspi.c need to a flag to pionts the address
|
||||
mask, So add the magic num '0xaa' into cmd[].
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
|
||||
drivers/mtd/spi/sf_internal.h | 7 ++++
|
||||
drivers/mtd/spi/spi_flash.c | 73 ++++++++++++++++++++++++++++++--------
|
||||
drivers/spi/fsl_qspi.c | 30 ++++++++++++++--
|
||||
include/configs/ls1012a_common.h | 3 +-
|
||||
5 files changed, 95 insertions(+), 20 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
|
||||
index 87a287a..2549c91 100644
|
||||
--- a/arch/arm/dts/fsl-ls1012a.dtsi
|
||||
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
|
||||
@@ -108,7 +108,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
- <0x0 0x40000000 0x0 0x4000000>;
|
||||
+ <0x0 0x40000000 0x0 0x8000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
num-cs = <2>;
|
||||
big-endian;
|
||||
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
|
||||
index c778b60..3c38425 100644
|
||||
--- a/drivers/mtd/spi/sf_internal.h
|
||||
+++ b/drivers/mtd/spi/sf_internal.h
|
||||
@@ -57,6 +57,13 @@ enum spi_nor_option_flags {
|
||||
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
|
||||
#define SPI_FLASH_16MB_BOUN 0x1000000
|
||||
|
||||
+#define SPI_FLASH_ADDR_MAGIC 0xaa
|
||||
+#define SPI_FLASH_ADDR_MAGIC_LEN 1
|
||||
+#define SPI_FLASH_4B_ADDR_LEN 4
|
||||
+#define SPI_FLASH_CMD_LEN_EXT (1 + SPI_FLASH_4B_ADDR_LEN + \
|
||||
+ SPI_FLASH_ADDR_MAGIC_LEN)
|
||||
+#define SPI_FLASH_64MB_BOUN 0x4000000
|
||||
+
|
||||
/* CFI Manufacture ID's */
|
||||
#define SPI_FLASH_CFI_MFR_SPANSION 0x01
|
||||
#define SPI_FLASH_CFI_MFR_STMICRO 0x20
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index 97e53c7..9d61ac0 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -21,12 +21,20 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
-static void spi_flash_addr(u32 addr, u8 *cmd)
|
||||
+static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
|
||||
{
|
||||
- /* cmd[0] is actual command */
|
||||
- cmd[1] = addr >> 16;
|
||||
- cmd[2] = addr >> 8;
|
||||
- cmd[3] = addr >> 0;
|
||||
+ if (offset_ext >= SPI_FLASH_16MB_BOUN) {
|
||||
+ /* cmd[0] is actual command */
|
||||
+ cmd[1] = addr >> 24;
|
||||
+ cmd[2] = addr >> 16;
|
||||
+ cmd[3] = addr >> 8;
|
||||
+ cmd[4] = addr >> 0;
|
||||
+ cmd[5] = SPI_FLASH_ADDR_MAGIC;
|
||||
+ } else {
|
||||
+ cmd[1] = addr >> 16;
|
||||
+ cmd[2] = addr >> 8;
|
||||
+ cmd[3] = addr >> 0;
|
||||
+ }
|
||||
}
|
||||
|
||||
/* Read commands array */
|
||||
@@ -302,9 +310,11 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
|
||||
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
{
|
||||
u32 erase_size, erase_addr;
|
||||
- u8 cmd[SPI_FLASH_CMD_LEN];
|
||||
+ u8 *cmd, cmdsz;
|
||||
int ret = -1;
|
||||
+ u32 offset_ext;
|
||||
|
||||
+ offset_ext = offset;
|
||||
erase_size = flash->erase_size;
|
||||
if (offset % erase_size || len % erase_size) {
|
||||
debug("SF: Erase offset/length not multiple of erase size\n");
|
||||
@@ -319,7 +329,18 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
}
|
||||
}
|
||||
|
||||
+ if (offset > SPI_FLASH_16MB_BOUN)
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ else
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+ cmd = calloc(1, cmdsz);
|
||||
+ if (!cmd) {
|
||||
+ debug("SF: Failed to allocate cmd\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+ memset(cmd, 0x0, cmdsz);
|
||||
cmd[0] = flash->erase_cmd;
|
||||
+
|
||||
while (len) {
|
||||
erase_addr = offset;
|
||||
|
||||
@@ -332,7 +353,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
#endif
|
||||
- spi_flash_addr(erase_addr, cmd);
|
||||
+ spi_flash_addr(erase_addr, cmd, offset_ext);
|
||||
|
||||
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
|
||||
cmd[2], cmd[3], erase_addr);
|
||||
@@ -347,6 +368,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
len -= erase_size;
|
||||
}
|
||||
|
||||
+ free(cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -356,9 +378,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
unsigned long byte_addr, page_size;
|
||||
u32 write_addr;
|
||||
size_t chunk_len, actual;
|
||||
- u8 cmd[SPI_FLASH_CMD_LEN];
|
||||
+ u8 *cmd, cmdsz;
|
||||
int ret = -1;
|
||||
+ u32 offset_ext;
|
||||
|
||||
+ offset_ext = offset;
|
||||
page_size = flash->page_size;
|
||||
|
||||
if (flash->flash_is_locked) {
|
||||
@@ -369,6 +393,16 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
}
|
||||
}
|
||||
|
||||
+ if (offset > SPI_FLASH_16MB_BOUN)
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ else
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+ cmd = calloc(1, cmdsz);
|
||||
+ if (!cmd) {
|
||||
+ debug("SF: Failed to allocate cmd\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+ memset(cmd, 0x0, cmdsz);
|
||||
cmd[0] = flash->write_cmd;
|
||||
for (actual = 0; actual < len; actual += chunk_len) {
|
||||
write_addr = offset;
|
||||
@@ -389,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
chunk_len = min(chunk_len,
|
||||
(size_t)flash->spi->max_write_size);
|
||||
|
||||
- spi_flash_addr(write_addr, cmd);
|
||||
+ spi_flash_addr(write_addr, cmd, offset_ext);
|
||||
|
||||
debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
|
||||
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
|
||||
@@ -404,6 +438,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
offset += chunk_len;
|
||||
}
|
||||
|
||||
+ free(cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -442,6 +477,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
u32 remain_len, read_len, read_addr;
|
||||
int bank_sel = 0;
|
||||
int ret = -1;
|
||||
+ u32 offset_ext;
|
||||
+
|
||||
+ offset_ext = offset;
|
||||
|
||||
/* Handle memory-mapped SPI */
|
||||
if (flash->memory_map) {
|
||||
@@ -456,15 +494,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
spi_release_bus(flash->spi);
|
||||
return 0;
|
||||
}
|
||||
-
|
||||
- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+ if (offset > SPI_FLASH_16MB_BOUN)
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ else
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
-
|
||||
+ memset(cmd, 0x0, cmdsz);
|
||||
cmd[0] = flash->read_cmd;
|
||||
+
|
||||
while (len) {
|
||||
read_addr = offset;
|
||||
|
||||
@@ -478,14 +519,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
return ret;
|
||||
bank_sel = flash->bank_curr;
|
||||
#endif
|
||||
- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
|
||||
+ if (offset_ext >= SPI_FLASH_16MB_BOUN) {
|
||||
+ remain_len = flash->size - offset;
|
||||
+ } else {
|
||||
+ remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
|
||||
(bank_sel + 1)) - offset;
|
||||
+ }
|
||||
if (len < remain_len)
|
||||
read_len = len;
|
||||
else
|
||||
read_len = remain_len;
|
||||
|
||||
- spi_flash_addr(read_addr, cmd);
|
||||
+ spi_flash_addr(read_addr, cmd, offset_ext);
|
||||
|
||||
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
|
||||
if (ret < 0) {
|
||||
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
|
||||
index 2b20038..09759fa 100644
|
||||
--- a/drivers/spi/fsl_qspi.c
|
||||
+++ b/drivers/spi/fsl_qspi.c
|
||||
@@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
|
||||
#define OFFSET_BITS_MASK GENMASK(23, 0)
|
||||
+/* the qspi contrller memmap space ,instead of flash space */
|
||||
+#define OFFSET_BITS_MASK_QSPI_SPACE GENMASK(27, 0)
|
||||
+#define SPI_FLASH_ADDR_EXT_MAGIC 0xaa
|
||||
|
||||
#define FLASH_STATUS_WEL 0x02
|
||||
|
||||
@@ -757,6 +760,13 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
|
||||
u32 bytes = DIV_ROUND_UP(bitlen, 8);
|
||||
static u32 wr_sfaddr;
|
||||
u32 txbuf;
|
||||
+ u8 offset_ext = 0;
|
||||
+ u32 flash_offset;
|
||||
+
|
||||
+ if (((u8 *)dout)[5] == SPI_FLASH_ADDR_EXT_MAGIC) {
|
||||
+ offset_ext = 1;
|
||||
+ memcpy(&flash_offset, dout + 1, 4);
|
||||
+ }
|
||||
|
||||
if (dout) {
|
||||
if (flags & SPI_XFER_BEGIN) {
|
||||
@@ -772,14 +782,28 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
|
||||
|
||||
if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
|
||||
priv->cur_seqid == QSPI_CMD_RDAR) {
|
||||
- priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||||
+ if (offset_ext)
|
||||
+ priv->sf_addr = swab32(flash_offset) &
|
||||
+ OFFSET_BITS_MASK_QSPI_SPACE;
|
||||
+ else
|
||||
+ priv->sf_addr = swab32(txbuf) &
|
||||
+ OFFSET_BITS_MASK;
|
||||
} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
|
||||
(priv->cur_seqid == QSPI_CMD_BE_4K)) {
|
||||
- priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||||
+ if (offset_ext)
|
||||
+ priv->sf_addr = swab32(flash_offset) &
|
||||
+ OFFSET_BITS_MASK_QSPI_SPACE;
|
||||
+ else
|
||||
+ priv->sf_addr = swab32(txbuf) &
|
||||
+ OFFSET_BITS_MASK;
|
||||
qspi_op_erase(priv);
|
||||
} else if (priv->cur_seqid == QSPI_CMD_PP ||
|
||||
priv->cur_seqid == QSPI_CMD_WRAR) {
|
||||
- wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||||
+ if (offset_ext)
|
||||
+ wr_sfaddr = swab32(flash_offset) &
|
||||
+ OFFSET_BITS_MASK_QSPI_SPACE;
|
||||
+ else
|
||||
+ wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||||
} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
|
||||
(priv->cur_seqid == QSPI_CMD_WREAR)) {
|
||||
#ifdef CONFIG_SPI_FLASH_BAR
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 3fd360a..150444d 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -63,9 +63,8 @@
|
||||
#define QSPI0_AMBA_BASE 0x40000000
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_DM_SPI_FLASH
|
||||
-#define CONFIG_SPI_FLASH_BAR
|
||||
|
||||
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
|
||||
+#define FSL_QSPI_FLASH_SIZE (1 << 26)
|
||||
#define FSL_QSPI_FLASH_NUM 2
|
||||
|
||||
/*
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,30 +0,0 @@ |
||||
From c67f214546a9d8ac00b9b947c145f4c032def8e2 Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Mon, 16 May 2016 14:39:52 +0800
|
||||
Subject: [PATCH 32/93] driver: spi: fsl_qspi: enable AHB read for qspi
|
||||
|
||||
If we don't enable the AHB read for ls1012a, input 'md 0x40000000',
|
||||
'md 0x41000000','md 0x42000000' address will be overlapped.
|
||||
After QSPI controller initialization for AHB, 'md 0x...' will access
|
||||
the whole QSPI flash address space.
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
include/configs/ls1012a_common.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 150444d..121824c 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -66,6 +66,7 @@
|
||||
|
||||
#define FSL_QSPI_FLASH_SIZE (1 << 26)
|
||||
#define FSL_QSPI_FLASH_NUM 2
|
||||
+#define CONFIG_SYS_FSL_QSPI_AHB
|
||||
|
||||
/*
|
||||
* Environment
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,47 +0,0 @@ |
||||
From 2daf451df50209e7626c2bf424d50ff23055784a Mon Sep 17 00:00:00 2001
|
||||
From: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Date: Wed, 18 May 2016 10:52:38 +0800
|
||||
Subject: [PATCH 33/93] mmc: fsl_esdhc: support two esdhc host controllers
|
||||
|
||||
This patch is to support two esdhc host controllers with
|
||||
the macro CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT.
|
||||
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
drivers/mmc/fsl_esdhc.c | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
|
||||
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
|
||||
index 7cc61a0..cacf879 100644
|
||||
--- a/drivers/mmc/fsl_esdhc.c
|
||||
+++ b/drivers/mmc/fsl_esdhc.c
|
||||
@@ -748,11 +748,26 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
|
||||
int fsl_esdhc_mmc_init(bd_t *bis)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg;
|
||||
+#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
|
||||
+ struct fsl_esdhc_cfg *cfg_1;
|
||||
+#endif
|
||||
|
||||
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
||||
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
||||
cfg->sdhc_clk = gd->arch.sdhc_clk;
|
||||
+#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
|
||||
+ cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
||||
+ cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
|
||||
+ cfg_1->sdhc_clk = gd->arch.sdhc_clk;
|
||||
+
|
||||
+ if (fsl_esdhc_initialize(bis, cfg))
|
||||
+ return -1;
|
||||
+ if (fsl_esdhc_initialize(bis, cfg_1))
|
||||
+ return -1;
|
||||
+ return 0;
|
||||
+#else
|
||||
return fsl_esdhc_initialize(bis, cfg);
|
||||
+#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,57 +0,0 @@ |
||||
From e3e641993a1a5148e71bdd3f7b3cb5da695b1632 Mon Sep 17 00:00:00 2001
|
||||
From: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Date: Fri, 20 May 2016 11:17:30 +0800
|
||||
Subject: [PATCH 34/93] mmc: fsl_esdhc: add workaround for non-removable card
|
||||
of esdhc-2
|
||||
|
||||
The esdhc-2 usually uses some on-board memory devices such as eMMC
|
||||
card or SDIO wifi module, and it doesn't support SDHC_CD_B. So we
|
||||
could only assume it always has a card instead of detecting SDHC_CD_B
|
||||
status. This patch is to add workaround for these non-removable
|
||||
cards which are used by esdhc-2.
|
||||
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
drivers/mmc/fsl_esdhc.c | 6 +++++-
|
||||
include/fsl_esdhc.h | 1 +
|
||||
2 files changed, 6 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
|
||||
index cacf879..2c6e175 100644
|
||||
--- a/drivers/mmc/fsl_esdhc.c
|
||||
+++ b/drivers/mmc/fsl_esdhc.c
|
||||
@@ -628,6 +628,8 @@ static int esdhc_getcd(struct mmc *mmc)
|
||||
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
||||
int timeout = 1000;
|
||||
|
||||
+ if (cfg->non_removable_card)
|
||||
+ return 1;
|
||||
#ifdef CONFIG_ESDHC_DETECT_QUIRK
|
||||
if (CONFIG_ESDHC_DETECT_QUIRK)
|
||||
return 1;
|
||||
@@ -759,7 +761,9 @@ int fsl_esdhc_mmc_init(bd_t *bis)
|
||||
cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
||||
cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
|
||||
cfg_1->sdhc_clk = gd->arch.sdhc_clk;
|
||||
-
|
||||
+#ifdef CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
+ cfg_1->non_removable_card = true;
|
||||
+#endif
|
||||
if (fsl_esdhc_initialize(bis, cfg))
|
||||
return -1;
|
||||
if (fsl_esdhc_initialize(bis, cfg_1))
|
||||
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
|
||||
index 073048f..8335106 100644
|
||||
--- a/include/fsl_esdhc.h
|
||||
+++ b/include/fsl_esdhc.h
|
||||
@@ -175,6 +175,7 @@ struct fsl_esdhc_cfg {
|
||||
#endif
|
||||
u32 sdhc_clk;
|
||||
u8 max_bus_width;
|
||||
+ bool non_removable_card;
|
||||
struct mmc_config cfg;
|
||||
};
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,43 +0,0 @@ |
||||
From 7d3d85483a6c4085de5c016b86838681e97e6577 Mon Sep 17 00:00:00 2001
|
||||
From: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Date: Fri, 20 May 2016 11:31:17 +0800
|
||||
Subject: [PATCH 35/93] armv8: ls1012a: enable two esdhc host controllers
|
||||
support
|
||||
|
||||
LS1012A chip has two esdhc host controllers, and this patch
|
||||
is to enable two controllers support for it.
|
||||
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
|
||||
include/configs/ls1012a_common.h | 2 ++
|
||||
2 files changed, 3 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index 24add1a..6918757 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -19,6 +19,7 @@
|
||||
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
+#define CONFIG_SYS_FSL_ESDHC_1_ADDR (CONFIG_SYS_IMMR + 0x00580000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 121824c..89d1370 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -94,6 +94,8 @@
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
+#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
|
||||
+#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,144 +0,0 @@ |
||||
From e70ae7f7ed00ecdbfa45fac3f342f1130df5029b Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Fri, 20 May 2016 16:37:34 +0800
|
||||
Subject: [PATCH 36/93] driver: spi: add exceed 16MB flash support
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 41 +++++++++++------------------------------
|
||||
1 file changed, 11 insertions(+), 30 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index 9d61ac0..e9d1c64 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -21,9 +21,9 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
-static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
|
||||
+static void spi_flash_addr(u32 addr, u8 *cmd)
|
||||
{
|
||||
- if (offset_ext >= SPI_FLASH_16MB_BOUN) {
|
||||
+ if (addr >= SPI_FLASH_16MB_BOUN) {
|
||||
/* cmd[0] is actual command */
|
||||
cmd[1] = addr >> 24;
|
||||
cmd[2] = addr >> 16;
|
||||
@@ -312,9 +312,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
u32 erase_size, erase_addr;
|
||||
u8 *cmd, cmdsz;
|
||||
int ret = -1;
|
||||
- u32 offset_ext;
|
||||
|
||||
- offset_ext = offset;
|
||||
erase_size = flash->erase_size;
|
||||
if (offset % erase_size || len % erase_size) {
|
||||
debug("SF: Erase offset/length not multiple of erase size\n");
|
||||
@@ -329,10 +327,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
}
|
||||
}
|
||||
|
||||
- if (offset > SPI_FLASH_16MB_BOUN)
|
||||
- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
- else
|
||||
- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
@@ -353,7 +348,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
#endif
|
||||
- spi_flash_addr(erase_addr, cmd, offset_ext);
|
||||
+ spi_flash_addr(erase_addr, cmd);
|
||||
|
||||
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
|
||||
cmd[2], cmd[3], erase_addr);
|
||||
@@ -380,9 +375,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
size_t chunk_len, actual;
|
||||
u8 *cmd, cmdsz;
|
||||
int ret = -1;
|
||||
- u32 offset_ext;
|
||||
|
||||
- offset_ext = offset;
|
||||
page_size = flash->page_size;
|
||||
|
||||
if (flash->flash_is_locked) {
|
||||
@@ -393,10 +386,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
}
|
||||
}
|
||||
|
||||
- if (offset > SPI_FLASH_16MB_BOUN)
|
||||
- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
- else
|
||||
- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
@@ -423,7 +413,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
chunk_len = min(chunk_len,
|
||||
(size_t)flash->spi->max_write_size);
|
||||
|
||||
- spi_flash_addr(write_addr, cmd, offset_ext);
|
||||
+ spi_flash_addr(write_addr, cmd);
|
||||
|
||||
debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
|
||||
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
|
||||
@@ -477,9 +467,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
u32 remain_len, read_len, read_addr;
|
||||
int bank_sel = 0;
|
||||
int ret = -1;
|
||||
- u32 offset_ext;
|
||||
-
|
||||
- offset_ext = offset;
|
||||
|
||||
/* Handle memory-mapped SPI */
|
||||
if (flash->memory_map) {
|
||||
@@ -494,10 +481,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
spi_release_bus(flash->spi);
|
||||
return 0;
|
||||
}
|
||||
- if (offset > SPI_FLASH_16MB_BOUN)
|
||||
- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
- else
|
||||
- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
@@ -508,7 +493,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
|
||||
while (len) {
|
||||
read_addr = offset;
|
||||
-
|
||||
#ifdef CONFIG_SF_DUAL_FLASH
|
||||
if (flash->dual_flash > SF_SINGLE_FLASH)
|
||||
spi_flash_dual(flash, &read_addr);
|
||||
@@ -519,18 +503,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
return ret;
|
||||
bank_sel = flash->bank_curr;
|
||||
#endif
|
||||
- if (offset_ext >= SPI_FLASH_16MB_BOUN) {
|
||||
- remain_len = flash->size - offset;
|
||||
- } else {
|
||||
- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
|
||||
+ remain_len = ((flash->size << flash->shift) *
|
||||
(bank_sel + 1)) - offset;
|
||||
- }
|
||||
+
|
||||
if (len < remain_len)
|
||||
read_len = len;
|
||||
else
|
||||
read_len = remain_len;
|
||||
|
||||
- spi_flash_addr(read_addr, cmd, offset_ext);
|
||||
+ spi_flash_addr(read_addr, cmd);
|
||||
|
||||
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
|
||||
if (ret < 0) {
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,60 +0,0 @@ |
||||
From 65a6669afc667dacacf24a3a3f340205e38b0c5d Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Fri, 27 May 2016 10:25:09 +0800
|
||||
Subject: [PATCH 37/93] driver: spi: remove Warning prints for Spansion FS-S
|
||||
fmaily
|
||||
|
||||
The Spansion flash FS-S family don't support the bank related
|
||||
commands, Even if flash size exceed 16MB, we cannot enable the
|
||||
macro CONFIG_SPI_FLASH_BAR. Also, we need remove the irrelevant
|
||||
warnings:
|
||||
"puts("SF: Warning - Only lower 16MiB accessible,"
|
||||
"Full access #define CONFIG_SPI_FLASH_BAR"
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 13 +++++++++----
|
||||
1 file changed, 9 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index e9d1c64..b0f09ab 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -1009,6 +1009,9 @@ int spi_flash_scan(struct spi_flash *flash)
|
||||
u8 idcode[5];
|
||||
u8 cmd;
|
||||
int ret;
|
||||
+#ifdef CONFIG_SPI_FLASH_SPANSION
|
||||
+ u8 id[6];
|
||||
+#endif
|
||||
|
||||
/* Read the ID codes */
|
||||
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
|
||||
@@ -1062,7 +1065,6 @@ int spi_flash_scan(struct spi_flash *flash)
|
||||
if ((jedec == 0x0219 || (jedec == 0x0220)) &&
|
||||
(ext_jedec & 0xff00) == 0x4d00) {
|
||||
int ret;
|
||||
- u8 id[6];
|
||||
|
||||
/* Read the ID codes again, 6 bytes */
|
||||
ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
|
||||
@@ -1253,10 +1255,13 @@ int spi_flash_scan(struct spi_flash *flash)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPI_FLASH_BAR
|
||||
- if (((flash->dual_flash == SF_SINGLE_FLASH) &&
|
||||
- (flash->size > SPI_FLASH_16MB_BOUN)) ||
|
||||
+ if ((id[5] != 0x81) &&
|
||||
+ /*Spansion FS-S family not support BAR ,
|
||||
+ Even if CONFIG_SPI_FLASH_BAR is unable, Need not the Warning prints */
|
||||
+ ((((flash->dual_flash == SF_SINGLE_FLASH) &&
|
||||
+ (flash->size > SPI_FLASH_16MB_BOUN))) ||
|
||||
((flash->dual_flash > SF_SINGLE_FLASH) &&
|
||||
- (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
|
||||
+ (flash->size > SPI_FLASH_16MB_BOUN << 1)))) {
|
||||
puts("SF: Warning - Only lower 16MiB accessible,");
|
||||
puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
|
||||
}
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,228 +0,0 @@ |
||||
From 8f096adfd96941e596b5fbf30a21193e32f2c1b0 Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Fri, 27 May 2016 15:10:40 +0530
|
||||
Subject: [PATCH 38/93] Shift board specific configurations
|
||||
|
||||
Board specific configurations are moved from
|
||||
ls1012a_common.h to ls1012aqds.h and ls1012ardb.h
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
---
|
||||
include/configs/ls1012a_common.h | 60 --------------------------------------
|
||||
include/configs/ls1012aqds.h | 58 ++++++++++++++++++++++++++++++++++++
|
||||
include/configs/ls1012ardb.h | 58 ++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 116 insertions(+), 60 deletions(-)
|
||||
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 89d1370..07ef7c6 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -88,66 +88,6 @@
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#endif /* CONFIG_EMU */
|
||||
|
||||
-/* MMC */
|
||||
-#if !defined(CONFIG_EMU)
|
||||
-#define CONFIG_MMC
|
||||
-#ifdef CONFIG_MMC
|
||||
-#define CONFIG_CMD_MMC
|
||||
-#define CONFIG_FSL_ESDHC
|
||||
-#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
|
||||
-#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
-#define CONFIG_GENERIC_MMC
|
||||
-#define CONFIG_CMD_FAT
|
||||
-#define CONFIG_DOS_PARTITION
|
||||
-#endif
|
||||
-#endif /* CONFIG_EMU */
|
||||
-
|
||||
-/* SATA */
|
||||
-#if !defined(CONFIG_EMU)
|
||||
-#define CONFIG_LIBATA
|
||||
-#define CONFIG_SCSI_AHCI
|
||||
-#define CONFIG_SCSI_AHCI_PLAT
|
||||
-#define CONFIG_CMD_SCSI
|
||||
-#define CONFIG_CMD_FAT
|
||||
-#define CONFIG_CMD_EXT2
|
||||
-#define CONFIG_DOS_PARTITION
|
||||
-#define CONFIG_BOARD_LATE_INIT
|
||||
-
|
||||
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
|
||||
-
|
||||
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
-#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
- CONFIG_SYS_SCSI_MAX_LUN)
|
||||
-
|
||||
-#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
-#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
|
||||
-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
|
||||
-
|
||||
-#define CONFIG_SYS_PCI_64BIT
|
||||
-
|
||||
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
|
||||
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
|
||||
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
|
||||
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
|
||||
-
|
||||
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
|
||||
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
|
||||
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
|
||||
-
|
||||
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
|
||||
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
|
||||
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
|
||||
-
|
||||
-#define CONFIG_NET_MULTI
|
||||
-#define CONFIG_PCI_PNP
|
||||
-#define CONFIG_E1000
|
||||
-#define CONFIG_PCI_SCAN_SHOW
|
||||
-#define CONFIG_CMD_PCI
|
||||
-#endif
|
||||
-
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index de998b8..488811b 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -26,6 +26,64 @@
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||
#endif
|
||||
|
||||
+/* MMC */
|
||||
+#if !defined(CONFIG_EMU)
|
||||
+#define CONFIG_MMC
|
||||
+#ifdef CONFIG_MMC
|
||||
+#define CONFIG_CMD_MMC
|
||||
+#define CONFIG_FSL_ESDHC
|
||||
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
+#define CONFIG_GENERIC_MMC
|
||||
+#define CONFIG_CMD_FAT
|
||||
+#define CONFIG_DOS_PARTITION
|
||||
+#endif
|
||||
+#endif /* CONFIG_EMU */
|
||||
+
|
||||
+/* SATA */
|
||||
+#if !defined(CONFIG_EMU)
|
||||
+#define CONFIG_LIBATA
|
||||
+#define CONFIG_SCSI_AHCI
|
||||
+#define CONFIG_SCSI_AHCI_PLAT
|
||||
+#define CONFIG_CMD_SCSI
|
||||
+#define CONFIG_CMD_FAT
|
||||
+#define CONFIG_CMD_EXT2
|
||||
+#define CONFIG_DOS_PARTITION
|
||||
+#define CONFIG_BOARD_LATE_INIT
|
||||
+
|
||||
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
|
||||
+
|
||||
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
+#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
+ CONFIG_SYS_SCSI_MAX_LUN)
|
||||
+
|
||||
+#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
+#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
|
||||
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
|
||||
+
|
||||
+#define CONFIG_SYS_PCI_64BIT
|
||||
+
|
||||
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
|
||||
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
|
||||
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
|
||||
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
|
||||
+
|
||||
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
|
||||
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
|
||||
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
|
||||
+
|
||||
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
|
||||
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
|
||||
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
|
||||
+
|
||||
+#define CONFIG_NET_MULTI
|
||||
+#define CONFIG_PCI_PNP
|
||||
+#define CONFIG_E1000
|
||||
+#define CONFIG_PCI_SCAN_SHOW
|
||||
+#define CONFIG_CMD_PCI
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* QIXIS Definitions
|
||||
*/
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index b40e02b..1629e19 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -55,6 +55,64 @@
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
#endif
|
||||
|
||||
+/* MMC */
|
||||
+#if !defined(CONFIG_EMU)
|
||||
+#define CONFIG_MMC
|
||||
+#ifdef CONFIG_MMC
|
||||
+#define CONFIG_CMD_MMC
|
||||
+#define CONFIG_FSL_ESDHC
|
||||
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
+#define CONFIG_GENERIC_MMC
|
||||
+#define CONFIG_CMD_FAT
|
||||
+#define CONFIG_DOS_PARTITION
|
||||
+#endif
|
||||
+#endif /* CONFIG_EMU */
|
||||
+
|
||||
+/* SATA */
|
||||
+#if !defined(CONFIG_EMU)
|
||||
+#define CONFIG_LIBATA
|
||||
+#define CONFIG_SCSI_AHCI
|
||||
+#define CONFIG_SCSI_AHCI_PLAT
|
||||
+#define CONFIG_CMD_SCSI
|
||||
+#define CONFIG_CMD_FAT
|
||||
+#define CONFIG_CMD_EXT2
|
||||
+#define CONFIG_DOS_PARTITION
|
||||
+#define CONFIG_BOARD_LATE_INIT
|
||||
+
|
||||
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
|
||||
+
|
||||
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
+#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
+ CONFIG_SYS_SCSI_MAX_LUN)
|
||||
+
|
||||
+#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
+#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
|
||||
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
|
||||
+
|
||||
+#define CONFIG_SYS_PCI_64BIT
|
||||
+
|
||||
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
|
||||
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
|
||||
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
|
||||
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
|
||||
+
|
||||
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
|
||||
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
|
||||
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
|
||||
+
|
||||
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
|
||||
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
|
||||
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
|
||||
+
|
||||
+#define CONFIG_NET_MULTI
|
||||
+#define CONFIG_PCI_PNP
|
||||
+#define CONFIG_E1000
|
||||
+#define CONFIG_PCI_SCAN_SHOW
|
||||
+#define CONFIG_CMD_PCI
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* I2C IO expander
|
||||
*/
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,566 +0,0 @@ |
||||
From 6aaa5973b9ae8452a546e0666b2389bb163fb949 Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Thu, 19 May 2016 16:45:27 +0530
|
||||
Subject: [PATCH 39/93] armv8: ls1012a: Add support of ls1012afrdm board
|
||||
|
||||
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
|
||||
development platform, with a complete debugging environment.
|
||||
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
|
||||
optimized to support the high-bandwidth DDR3L memory and
|
||||
a full complement of high-speed SerDes ports.
|
||||
|
||||
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
---
|
||||
arch/arm/Kconfig | 10 ++
|
||||
arch/arm/dts/Makefile | 3 +-
|
||||
arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++
|
||||
arch/arm/dts/fsl-ls1012a-frdm.dtsi | 39 ++++++
|
||||
board/freescale/ls1012afrdm/Kconfig | 15 +++
|
||||
board/freescale/ls1012afrdm/MAINTAINERS | 6 +
|
||||
board/freescale/ls1012afrdm/Makefile | 7 ++
|
||||
board/freescale/ls1012afrdm/README | 94 +++++++++++++++
|
||||
board/freescale/ls1012afrdm/ls1012afrdm.c | 183 +++++++++++++++++++++++++++++
|
||||
configs/ls1012afrdm_qspi_defconfig | 10 ++
|
||||
include/configs/ls1012afrdm.h | 59 ++++++++++
|
||||
11 files changed, 441 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
|
||||
create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
|
||||
create mode 100644 board/freescale/ls1012afrdm/Kconfig
|
||||
create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
|
||||
create mode 100644 board/freescale/ls1012afrdm/Makefile
|
||||
create mode 100644 board/freescale/ls1012afrdm/README
|
||||
create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
create mode 100644 configs/ls1012afrdm_qspi_defconfig
|
||||
create mode 100644 include/configs/ls1012afrdm.h
|
||||
|
||||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
|
||||
index b536684..23fce38 100644
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -669,6 +669,15 @@ config TARGET_LS1012ARDB
|
||||
development platform that supports the QorIQ LS1012A
|
||||
Layerscape Architecture processor.
|
||||
|
||||
+config TARGET_LS1012AFRDM
|
||||
+ bool "Support ls1012afrdm"
|
||||
+ select ARM64
|
||||
+ help
|
||||
+ Support for Freescale LS1012AFRDM platform.
|
||||
+ The LS1012A Freedom board (FRDM) is a high-performance
|
||||
+ development platform that supports the QorIQ LS1012A
|
||||
+ Layerscape Architecture processor.
|
||||
+
|
||||
config TARGET_LS1021AQDS
|
||||
bool "Support ls1021aqds"
|
||||
select CPU_V7
|
||||
@@ -816,6 +825,7 @@ source "board/freescale/ls1021atwr/Kconfig"
|
||||
source "board/freescale/ls1043ardb/Kconfig"
|
||||
source "board/freescale/ls1012aqds/Kconfig"
|
||||
source "board/freescale/ls1012ardb/Kconfig"
|
||||
+source "board/freescale/ls1012afrdm/Kconfig"
|
||||
source "board/freescale/mx23evk/Kconfig"
|
||||
source "board/freescale/mx25pdk/Kconfig"
|
||||
source "board/freescale/mx28evk/Kconfig"
|
||||
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
|
||||
index 9e8137b..de023b4 100644
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -96,7 +96,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
|
||||
fsl-ls1043a-qds-lpuart.dtb \
|
||||
fsl-ls1043a-rdb.dtb \
|
||||
fsl-ls1012a-qds.dtb \
|
||||
- fsl-ls1012a-rdb.dtb
|
||||
+ fsl-ls1012a-rdb.dtb \
|
||||
+ fsl-ls1012a-frdm.dtb
|
||||
|
||||
dtb-$(CONFIG_MACH_SUN4I) += \
|
||||
sun4i-a10-a1000.dtb \
|
||||
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
|
||||
new file mode 100644
|
||||
index 0000000..3a06c0a
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
|
||||
@@ -0,0 +1,16 @@
|
||||
+/*
|
||||
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
|
||||
+ *
|
||||
+ * Copyright (C) 2016, Freescale Semiconductor
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "fsl-ls1012a-frdm.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &duart0;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
|
||||
new file mode 100644
|
||||
index 0000000..9f0db91
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
|
||||
@@ -0,0 +1,39 @@
|
||||
+/*
|
||||
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
|
||||
+ *
|
||||
+ * Copyright (C) 2016, Freescale Semiconductor
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+
|
||||
+/include/ "fsl-ls1012a.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "LS1012A FREEDOM Board";
|
||||
+ aliases {
|
||||
+ spi0 = &qspi;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&qspi {
|
||||
+ bus-num = <0>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ qflash0: s25fl128s@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "spi-flash";
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&duart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000..a34521c
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012afrdm/Kconfig
|
||||
@@ -0,0 +1,15 @@
|
||||
+if TARGET_LS1012AFRDM
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "ls1012afrdm"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "freescale"
|
||||
+
|
||||
+config SYS_SOC
|
||||
+ default "fsl-layerscape"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "ls1012afrdm"
|
||||
+
|
||||
+endif
|
||||
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
|
||||
new file mode 100644
|
||||
index 0000000..2f31d0f
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
|
||||
@@ -0,0 +1,6 @@
|
||||
+LS1012AFRDM BOARD
|
||||
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
+S: Maintained
|
||||
+F: board/freescale/ls1012afrdm/
|
||||
+F: include/configs/ls1012afrdm.h
|
||||
+F: configs/ls1012afrdm_defconfig
|
||||
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
|
||||
new file mode 100644
|
||||
index 0000000..dbfa2ce
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012afrdm/Makefile
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+obj-y += ls1012afrdm.o
|
||||
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
|
||||
new file mode 100644
|
||||
index 0000000..0aadbb1
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012afrdm/README
|
||||
@@ -0,0 +1,94 @@
|
||||
+Overview
|
||||
+--------
|
||||
+The LS1012AFRDM power supplies (PS) provide all the voltages necessary
|
||||
+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
|
||||
+and other onboard peripherals.
|
||||
+
|
||||
+LS1012A SoC Overview
|
||||
+--------------------
|
||||
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
|
||||
+A53 processor, with 32 KB of parity protected L1-I cache,
|
||||
+32 KB of ECC protected L1-D cache, as well as 256 KB of
|
||||
+ECC protected L2 cache.
|
||||
+
|
||||
+The LS1012A SoC includes the following function and features:
|
||||
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
|
||||
+ - ARM v8 cryptography extensions
|
||||
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
|
||||
+ 16-/8-bit operation (no ECC support)
|
||||
+ - ARM core-link CCI-400 cache coherent interconnect
|
||||
+ - Packet Forwarding Engine (PFE)
|
||||
+ - Cryptography acceleration (SEC)
|
||||
+ - Ethernet interfaces supported by PFE:
|
||||
+ - One Configurable x3 SerDes:
|
||||
+ Two Serdes PLLs supported for usage by any SerDes data lane
|
||||
+ Support for up to 6 GBaud operation
|
||||
+ - High-speed peripheral interfaces:
|
||||
+ - One PCI Express Gen2 controller, supporting x1 operation
|
||||
+ - One serial ATA (SATA Gen 3.0) controller
|
||||
+ - One USB 3.0/2.0 controller with integrated PHY
|
||||
+ - One USB 2.0 controller with ULPI interface. .
|
||||
+ - Additional peripheral interfaces:
|
||||
+ - One quad serial peripheral interface (QuadSPI) controller
|
||||
+ - One serial peripheral interface (SPI) controller
|
||||
+ - Two enhanced secure digital host controllers
|
||||
+ - Two I2C controllers
|
||||
+ - One 16550 compliant DUART (two UART interfaces)
|
||||
+ - Two general purpose IOs (GPIO)
|
||||
+ - Two FlexTimers
|
||||
+ - Five synchronous audio interfaces (SAI)
|
||||
+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
|
||||
+ - Single-source clocking solution enabling generation of core, platform,
|
||||
+ DDR, SerDes, and USB clocks from a single external crystal and internal
|
||||
+ crystaloscillator
|
||||
+ - Thermal monitor unit (TMU) with +/- 3C accuracy
|
||||
+ - Two WatchDog timers
|
||||
+ - ARM generic timer
|
||||
+ - QorIQ platform's trust architecture 2.1
|
||||
+
|
||||
+ LS1012AFRDM board Overview
|
||||
+ -----------------------
|
||||
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
|
||||
+ - 2 SGMII 1G PHYs
|
||||
+ - DDR Controller
|
||||
+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
|
||||
+ operating at 1.35 V
|
||||
+ - QSPI
|
||||
+ - Onboard 512 Mbit QSPI flash memory running at speed up
|
||||
+ to 108/54 MHz
|
||||
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
|
||||
+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
|
||||
+ Micro-AB connector.
|
||||
+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
|
||||
+ as a Micro-AB device.
|
||||
+ - I2C controller
|
||||
+ - One I2C bus with connectivity to Arduino headers
|
||||
+ - UART
|
||||
+ - UART (Console): UART1 (Without flow control) for console
|
||||
+ - ARM JTAG support
|
||||
+ - ARM Cortex® 10-pin JTAG connector for LS1012A
|
||||
+ - CMSIS DAP through K20 microcontroller
|
||||
+ - SAI Audio interface
|
||||
+ - One SAI port, SAI 2 with full duplex support
|
||||
+ - Clocks
|
||||
+ - 25 MHz crystal for LS1012A
|
||||
+ - 8 MHz Crystal for K20
|
||||
+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
|
||||
+ - Power Supplies
|
||||
+ - 5 V input supply from USB
|
||||
+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
|
||||
+ other board interfaces
|
||||
+
|
||||
+Booting Options
|
||||
+---------------
|
||||
+a) QSPI Flash 1
|
||||
+
|
||||
+QSPI flash map
|
||||
+--------------
|
||||
+Images | Size |QSPI Flash Address
|
||||
+------------------------------------------
|
||||
+RCW + PBI | 1MB | 0x4000_0000
|
||||
+U-boot | 1MB | 0x4010_0000
|
||||
+U-boot Env | 1MB | 0x4020_0000
|
||||
+PPA FIT image | 2MB | 0x4050_0000
|
||||
+Linux ITB | ~53MB | 0x40A0_0000
|
||||
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
new file mode 100644
|
||||
index 0000000..6be8951
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
@@ -0,0 +1,183 @@
|
||||
+/*
|
||||
+ * Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <i2c.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <asm/arch/clock.h>
|
||||
+#include <asm/arch/fsl_serdes.h>
|
||||
+#include <asm/arch/ppa.h>
|
||||
+#include <asm/arch/soc.h>
|
||||
+#include <hwconfig.h>
|
||||
+#include <ahci.h>
|
||||
+#include <mmc.h>
|
||||
+#include <scsi.h>
|
||||
+#include <fsl_csu.h>
|
||||
+#include <fsl_esdhc.h>
|
||||
+#include <environment.h>
|
||||
+#include <fsl_mmdc.h>
|
||||
+#include <netdev.h>
|
||||
+
|
||||
+DECLARE_GLOBAL_DATA_PTR;
|
||||
+
|
||||
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
|
||||
+{
|
||||
+ int timeout = 1000;
|
||||
+
|
||||
+ out_be32(ptr, value);
|
||||
+
|
||||
+ while (in_be32(ptr) & bits) {
|
||||
+ udelay(100);
|
||||
+ timeout--;
|
||||
+ }
|
||||
+ if (timeout <= 0)
|
||||
+ puts("Error: wait for clear timeout.\n");
|
||||
+}
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ puts("Board: LS1012AFRDM ");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void mmdc_init(void)
|
||||
+{
|
||||
+ struct mmdc_p_regs *mmdc =
|
||||
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
+
|
||||
+ /* Set MMDC_MDSCR[CON_REQ] */
|
||||
+ out_be32(&mmdc->mdscr, 0x00008000);
|
||||
+
|
||||
+ /* configure timing parms */
|
||||
+ out_be32(&mmdc->mdotc, 0x12554000);
|
||||
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
+ out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
+
|
||||
+ /* other parms */
|
||||
+ out_be32(&mmdc->mdmisc, 0x00000680);
|
||||
+ out_be32(&mmdc->mpmur0, 0x00000800);
|
||||
+ out_be32(&mmdc->mdrwd, 0x00002000);
|
||||
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
+
|
||||
+ /* out of reset delays */
|
||||
+ out_be32(&mmdc->mdor, 0x00bf1023);
|
||||
+
|
||||
+ /* physical parms */
|
||||
+ out_be32(&mmdc->mdctl, 0x04180000);
|
||||
+ out_be32(&mmdc->mdasp, 0x0000007f);
|
||||
+
|
||||
+ /* Enable MMDC */
|
||||
+ out_be32(&mmdc->mdctl, 0x84180000);
|
||||
+
|
||||
+ /* dram init sequence: update MRs */
|
||||
+ out_be32(&mmdc->mdscr, 0x00088032);
|
||||
+ out_be32(&mmdc->mdscr, 0x00008033);
|
||||
+ out_be32(&mmdc->mdscr, 0x00048031);
|
||||
+ out_be32(&mmdc->mdscr, 0x19308030);
|
||||
+
|
||||
+ /* dram init sequence: ZQCL */
|
||||
+ out_be32(&mmdc->mdscr, 0x04008040);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
|
||||
+
|
||||
+ /* Calibrations now: wr lvl */
|
||||
+ out_be32(&mmdc->mdscr, 0x00848031);
|
||||
+ out_be32(&mmdc->mdscr, 0x00008200);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
|
||||
+
|
||||
+ mdelay(1);
|
||||
+
|
||||
+ out_be32(&mmdc->mdscr, 0x00048031);
|
||||
+ out_be32(&mmdc->mdscr, 0x00008000);
|
||||
+
|
||||
+ mdelay(1);
|
||||
+
|
||||
+ /* Calibrations now: Read DQS gating calibration */
|
||||
+ out_be32(&mmdc->mdscr, 0x04008050);
|
||||
+ out_be32(&mmdc->mdscr, 0x00048033);
|
||||
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
+ out_be32(&mmdc->mprddlctl, 0x40404040);
|
||||
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
|
||||
+
|
||||
+ out_be32(&mmdc->mdscr, 0x00008033);
|
||||
+
|
||||
+ /* Calibrations now: Read calibration */
|
||||
+ out_be32(&mmdc->mdscr, 0x04008050);
|
||||
+ out_be32(&mmdc->mdscr, 0x00048033);
|
||||
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
|
||||
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
|
||||
+
|
||||
+ out_be32(&mmdc->mdscr, 0x00008033);
|
||||
+
|
||||
+ /* PD, SR */
|
||||
+ out_be32(&mmdc->mdpdc, 0x00030035);
|
||||
+ out_be32(&mmdc->mapsr, 0x00001067);
|
||||
+
|
||||
+ /* refresh scheme */
|
||||
+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
|
||||
+
|
||||
+ /* disable CON_REQ */
|
||||
+ out_be32(&mmdc->mdscr, 0x0);
|
||||
+}
|
||||
+
|
||||
+int dram_init(void)
|
||||
+{
|
||||
+ mmdc_init();
|
||||
+
|
||||
+ gd->ram_size = 0x20000000;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int board_eth_init(bd_t *bis)
|
||||
+{
|
||||
+ return pci_eth_init(bis);
|
||||
+}
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ fsl_lsch2_early_init_f();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int board_init(void)
|
||||
+{
|
||||
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
+ /*
|
||||
+ * Set CCI-400 control override register to enable barrier
|
||||
+ * transaction
|
||||
+ */
|
||||
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
||||
+
|
||||
+#ifdef CONFIG_ENV_IS_NOWHERE
|
||||
+ gd->env_addr = (ulong)&default_environment[0];
|
||||
+#endif
|
||||
+
|
||||
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
|
||||
+ enable_layerscape_ns_access();
|
||||
+#endif
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int ft_board_setup(void *blob, bd_t *bd)
|
||||
+{
|
||||
+ u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
+ u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
+
|
||||
+ /* fixup DT for the two DDR banks */
|
||||
+ base[0] = gd->bd->bi_dram[0].start;
|
||||
+ size[0] = gd->bd->bi_dram[0].size;
|
||||
+ base[1] = gd->bd->bi_dram[1].start;
|
||||
+ size[1] = gd->bd->bi_dram[1].size;
|
||||
+
|
||||
+ fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
+ ft_cpu_setup(blob, bd);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
|
||||
new file mode 100644
|
||||
index 0000000..e27181c
|
||||
--- /dev/null
|
||||
+++ b/configs/ls1012afrdm_qspi_defconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TARGET_LS1012AFRDM=y
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
+# CONFIG_CMD_IMLS is not set
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
|
||||
+CONFIG_OF_CONTROL=y
|
||||
+CONFIG_DM=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_DM_SPI=y
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
new file mode 100644
|
||||
index 0000000..3231ab7
|
||||
--- /dev/null
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -0,0 +1,59 @@
|
||||
+/*
|
||||
+ * Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __LS1012ARDB_H__
|
||||
+#define __LS1012ARDB_H__
|
||||
+
|
||||
+#include "ls1012a_common.h"
|
||||
+
|
||||
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
+#define CONFIG_NR_DRAM_BANKS 2
|
||||
+
|
||||
+#define CONFIG_CMD_MEMINFO
|
||||
+#define CONFIG_CMD_MEMTEST
|
||||
+#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
+
|
||||
+#define CONFIG_PHYLIB
|
||||
+#define CONFIG_PHY_REALTEK
|
||||
+/*
|
||||
+* USB
|
||||
+*/
|
||||
+#define CONFIG_HAS_FSL_XHCI_USB
|
||||
+
|
||||
+#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
+#define CONFIG_USB_XHCI
|
||||
+#define CONFIG_USB_XHCI_FSL
|
||||
+#define CONFIG_USB_XHCI_DWC3
|
||||
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
+#define CONFIG_CMD_USB
|
||||
+#define CONFIG_USB_STORAGE
|
||||
+#define CONFIG_CMD_EXT2
|
||||
+
|
||||
+#define CONFIG_USB_DWC3
|
||||
+#define CONFIG_USB_DWC3_GADGET
|
||||
+
|
||||
+#define CONFIG_USB_GADGET
|
||||
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
+#define CONFIG_USB_GADGET_DOWNLOAD
|
||||
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
||||
+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
|
||||
+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
|
||||
+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
|
||||
+#define CONFIG_USB_GADGET_DUALSPEED
|
||||
+
|
||||
+/* USB Gadget ums command */
|
||||
+#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
+#endif
|
||||
+
|
||||
+#define CONFIG_CMD_MEMINFO
|
||||
+#define CONFIG_CMD_MEMTEST
|
||||
+#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
+
|
||||
+#endif /* __LS1012ARDB_H__ */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,36 +0,0 @@ |
||||
From 0bfcfaafa23af0e8c9ae9df3236831fcaaa597b8 Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Mon, 4 Apr 2016 15:07:47 +0530
|
||||
Subject: [PATCH 40/93] DNCPE-138 CSU config for PFE
|
||||
|
||||
Configure PFE for NS access.
|
||||
|
||||
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
index 2fd33e1..5250ac7 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
|
||||
@@ -25,6 +25,7 @@ enum csu_cslx_ind {
|
||||
CSU_CSLX_PCIE3_IO,
|
||||
CSU_CSLX_USB3 = 20,
|
||||
CSU_CSLX_USB2,
|
||||
+ CSU_CSLX_PFE = 23,
|
||||
CSU_CSLX_SERDES = 32,
|
||||
CSU_CSLX_QDMA,
|
||||
CSU_CSLX_LPUART2,
|
||||
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
|
||||
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB3, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB2, CSU_ALL_RW},
|
||||
+ {CSU_CSLX_PFE, CSU_ALL_RW},
|
||||
{CSU_CSLX_SERDES, CSU_ALL_RW},
|
||||
{CSU_CSLX_QDMA, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART2, CSU_ALL_RW},
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,69 +0,0 @@ |
||||
From 63acb257c32bd86abbad5abcc002d6c78b72f0ab Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Mon, 16 May 2016 20:21:38 +0530
|
||||
Subject: [PATCH 42/93] DNCPE-138 Rest external PHYs
|
||||
|
||||
Need to reset external PHYs through IO expander for proper function.
|
||||
|
||||
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012ardb/eth.c | 14 ++++++++++++++
|
||||
include/configs/ls1012ardb.h | 9 +++++++++
|
||||
2 files changed, 23 insertions(+)
|
||||
|
||||
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
|
||||
index 29830e8..24fdd83 100644
|
||||
--- a/board/freescale/ls1012ardb/eth.c
|
||||
+++ b/board/freescale/ls1012ardb/eth.c
|
||||
@@ -20,6 +20,20 @@
|
||||
|
||||
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
||||
|
||||
+
|
||||
+void reset_phy(void)
|
||||
+{
|
||||
+
|
||||
+ /*Through reset IO expander reset both RGMII and SGMII PHYs */
|
||||
+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 6, __PHY_MASK);
|
||||
+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, __PHY_ETH2_MASK);
|
||||
+ mdelay(10);
|
||||
+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, __PHY_ETH1_MASK);
|
||||
+ mdelay(10);
|
||||
+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, 0xFF);
|
||||
+ mdelay(50);
|
||||
+}
|
||||
+
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_FSL_PPFE
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index 1b72bf1..23722e0 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -24,6 +24,7 @@
|
||||
#define EMAC2_PHY_ADDR 0x1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_REALTEK
|
||||
+#define CONFIG_RESET_PHY_R
|
||||
#endif
|
||||
|
||||
/*
|
||||
@@ -128,6 +129,14 @@
|
||||
#define __SW_REV_A 0xF8
|
||||
#define __SW_REV_B 0xF0
|
||||
|
||||
+/*
|
||||
+ *I2C RESET expander
|
||||
+ */
|
||||
+#define CONFIG_SYS_I2C_RESET_IO_EXPANDER 0x25
|
||||
+#define __PHY_MASK 0xF9
|
||||
+#define __PHY_ETH2_MASK 0xFB
|
||||
+#define __PHY_ETH1_MASK 0xFD
|
||||
+
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,334 +0,0 @@ |
||||
From b17d75d2c1dc6cd1d55bcddbf7d3d4242e85e88e Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Fri, 20 May 2016 15:25:12 +0530
|
||||
Subject: [PATCH 43/93] DNCPE-296 PFE reset workaround
|
||||
|
||||
LS1012A PFE doesn't have global reset control.
|
||||
Due to this Linux pfe doesn't work when it was started at U-boot
|
||||
This patch provides U-boot command to stop pfe, that should be used before starting Linux.
|
||||
|
||||
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
common/cmd_pfe_commands.c | 83 +++++++++++++++++++++++++++++++++++-
|
||||
drivers/net/pfe_eth/pfe/cbus/hif.h | 3 ++
|
||||
drivers/net/pfe_eth/pfe/pfe.h | 2 +
|
||||
drivers/net/pfe_eth/pfe_driver.c | 58 ++++++++++++++++++++-----
|
||||
drivers/net/pfe_eth/pfe_eth.c | 6 +--
|
||||
5 files changed, 136 insertions(+), 16 deletions(-)
|
||||
|
||||
diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
|
||||
index f9f92c7..0e22097 100644
|
||||
--- a/common/cmd_pfe_commands.c
|
||||
+++ b/common/cmd_pfe_commands.c
|
||||
@@ -35,6 +35,7 @@
|
||||
#include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
+void hif_rx_desc_disable(void);
|
||||
int pfe_load_elf(int pe_mask, const struct firmware *fw);
|
||||
int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
|
||||
|
||||
@@ -593,7 +594,9 @@ void bmu(int id, void *base)
|
||||
}
|
||||
|
||||
#define PESTATUS_ADDR_CLASS 0x800
|
||||
+#define PEMBOX_ADDR_CLASS 0x890
|
||||
#define PESTATUS_ADDR_TMU 0x80
|
||||
+#define PEMBOX_ADDR_TMU 0x290
|
||||
#define PESTATUS_ADDR_UTIL 0x0
|
||||
|
||||
static void pfe_pe_status(int argc, char * const argv[])
|
||||
@@ -857,7 +860,6 @@ void hif_rx_enable(void)
|
||||
void hif_rx_disable(void)
|
||||
}
|
||||
#endif
|
||||
-
|
||||
#define ROUTE_TABLE_START (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
|
||||
static void pfe_command_fftest(int argc, char * const argv[])
|
||||
{
|
||||
@@ -865,7 +867,6 @@ static void pfe_command_fftest(int argc, char * const argv[])
|
||||
struct eth_device *edev_eth0;
|
||||
struct eth_device *edev_eth1;
|
||||
|
||||
-
|
||||
// open eth0 and eth1
|
||||
edev_eth0 = eth_get_dev_by_name("pfe_eth0");
|
||||
if (!edev_eth0)
|
||||
@@ -916,6 +917,80 @@ static void pfe_command_start(int argc, char * const argv[])
|
||||
}
|
||||
#endif
|
||||
|
||||
+#ifdef PFE_LS1012A_RESET_WA
|
||||
+/*This function sends a dummy packet to HIF through TMU3 */
|
||||
+static void send_dummy_pkt_to_hif(void)
|
||||
+{
|
||||
+ u32 buf;
|
||||
+ static u32 dummy_pkt[] = {
|
||||
+ 0x4200800a, 0x01000003, 0x00018100, 0x00000000,
|
||||
+ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
|
||||
+ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
|
||||
+ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
|
||||
+ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
|
||||
+
|
||||
+ /*Allocate BMU2 buffer */
|
||||
+ buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
|
||||
+
|
||||
+ printf("Sending a dummy pkt to HIF %x\n", buf);
|
||||
+ buf += 0x80;
|
||||
+ memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
|
||||
+ /*Write length and pkt to TMU*/
|
||||
+ writel(0x03000042, TMU_PHY_INQ_PKTPTR);
|
||||
+ writel(buf, TMU_PHY_INQ_PKTINFO);
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static void pfe_command_stop(int argc, char * const argv[])
|
||||
+{
|
||||
+ int id;
|
||||
+ u32 rx_status;
|
||||
+ printf("Stopping PFE \n");
|
||||
+
|
||||
+ /*Mark all descriptors as LAST_BD */
|
||||
+ hif_rx_desc_disable();
|
||||
+
|
||||
+ /*If HIF Rx BDP is busy send a dummy packet */
|
||||
+ rx_status = readl(HIF_RX_STATUS);
|
||||
+ printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
|
||||
+ if(rx_status & BDP_CSR_RX_DMA_ACTV)
|
||||
+ send_dummy_pkt_to_hif();
|
||||
+ udelay(10);
|
||||
+
|
||||
+ if(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
|
||||
+ printf("Unable to stop HIF\n");
|
||||
+
|
||||
+ /*Disable Class PEs */
|
||||
+
|
||||
+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
|
||||
+ {
|
||||
+ printf("Stop %d\n", id);
|
||||
+ /*Inform PE to stop */
|
||||
+ pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
|
||||
+ udelay(10);
|
||||
+
|
||||
+ printf("Reading %d\n", id);
|
||||
+ /*Read status */
|
||||
+ if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
|
||||
+ printf("Failed to stop PE%d\n", id);
|
||||
+ }
|
||||
+ /*Disable TMU PEs */
|
||||
+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++)
|
||||
+ {
|
||||
+ if(id == TMU2_ID) continue;
|
||||
+
|
||||
+ printf("Stop %d\n", id);
|
||||
+ /*Inform PE to stop */
|
||||
+ pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
|
||||
+ udelay(10);
|
||||
+
|
||||
+ printf("Reading %d\n", id);
|
||||
+ /*Read status */
|
||||
+ if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
|
||||
+ printf("Failed to stop PE%d\n", id);
|
||||
+ }
|
||||
+}
|
||||
+#endif
|
||||
|
||||
static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
@@ -965,6 +1040,10 @@ static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
else if (strcmp(argv[1], "start") == 0)
|
||||
pfe_command_start(argc, argv);
|
||||
#endif
|
||||
+#ifdef PFE_LS1012A_RESET_WA
|
||||
+ else if (strcmp(argv[1], "stop") == 0)
|
||||
+ pfe_command_stop(argc, argv);
|
||||
+#endif
|
||||
else
|
||||
{
|
||||
printf("Unknown option: %s\n", argv[1]);
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
|
||||
index a4dd7c2..2329faa 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/hif.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
|
||||
@@ -34,6 +34,9 @@
|
||||
#define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1)
|
||||
#define HIF_CTRL_BDP_CH_START_WSTB (1<<2)
|
||||
|
||||
+/*HIF_RX_STATUS bits */
|
||||
+#define BDP_CSR_RX_DMA_ACTV (1<<16)
|
||||
+
|
||||
/*HIF_INT_ENABLE bits */
|
||||
#define HIF_INT_EN (1 << 0)
|
||||
#define HIF_RXBD_INT_EN (1 << 1)
|
||||
diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
|
||||
index e8e2221..6994a20 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/pfe.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/pfe.h
|
||||
@@ -1,6 +1,8 @@
|
||||
#ifndef _PFE_H_
|
||||
#define _PFE_H_
|
||||
|
||||
+#define PFE_LS1012A_RESET_WA
|
||||
+
|
||||
#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
|
||||
#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
|
||||
#define CLASS_DMEM_SIZE 0x00002000
|
||||
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
|
||||
index ca00e98..b06a352 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_driver.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_driver.c
|
||||
@@ -51,13 +51,18 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
struct rx_desc_s *rx_desc = g_rx_desc;
|
||||
struct bufDesc *bd;
|
||||
int len = -1;
|
||||
- //volatile u32 ctrl;
|
||||
+ volatile u32 ctrl;
|
||||
struct hif_header_s *hif_header;
|
||||
|
||||
bd = rx_desc->rxBase + rx_desc->rxToRead;
|
||||
|
||||
- if (bd->ctrl & BD_CTRL_DESC_EN)
|
||||
+ if (bd->ctrl & BD_CTRL_DESC_EN) {
|
||||
+ if(!(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)){
|
||||
+ /*If BDP is not active give write strobe */
|
||||
+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
|
||||
+ }
|
||||
return len; //No pending Rx packet
|
||||
+ }
|
||||
|
||||
/* this len include hif_header(8bytes) */
|
||||
len = bd->ctrl & 0xFFFF;
|
||||
@@ -69,7 +74,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
|
||||
hif_header, len, hif_header->port_no, bd->status);
|
||||
|
||||
-#if 0
|
||||
+#if DEBUG
|
||||
{
|
||||
int i;
|
||||
unsigned char *p = (unsigned char *)hif_header;
|
||||
@@ -85,20 +90,26 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
*pkt_ptr = (unsigned int )(hif_header + 1);
|
||||
*phy_port = hif_header->port_no;
|
||||
len -= sizeof(struct hif_header_s);
|
||||
-#if 0
|
||||
+
|
||||
+#if defined(PFE_LS1012A_RESET_WA)
|
||||
/* reset bd control field */
|
||||
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
|
||||
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
|
||||
+#else
|
||||
+ /* reset bd control field */
|
||||
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
|
||||
+ /* If we use BD_CTRL_LAST_BD, rxToRead never changes */
|
||||
+ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
|
||||
+#endif
|
||||
bd->ctrl = ctrl;
|
||||
bd->status = 0;
|
||||
|
||||
- rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
|
||||
|
||||
/* Give START_STROBE to BDP to fetch the descriptor __NOW__,
|
||||
* BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
|
||||
* In idle state (ie., no rx pkt), BDP will not fetch
|
||||
* the descriptor even if strobe is given(I think) */
|
||||
writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
|
||||
-#endif
|
||||
+
|
||||
return len;
|
||||
}
|
||||
|
||||
@@ -298,14 +309,37 @@ void hif_rx_desc_dump(void)
|
||||
rx_desc = g_rx_desc;
|
||||
bd_va = rx_desc->rxBase;
|
||||
|
||||
- printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
|
||||
+ dprint("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
|
||||
for (i=0; i < rx_desc->rxRingSize; i++) {
|
||||
-// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
|
||||
-// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
|
||||
+ dprint("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
|
||||
+ bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
|
||||
+ bd_va++;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/** This function mark all Rx descriptors as LAST_BD.
|
||||
+ */
|
||||
+void hif_rx_desc_disable(void)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct rx_desc_s *rx_desc;
|
||||
+ struct bufDesc *bd_va;
|
||||
+
|
||||
+ if (g_rx_desc == NULL) {
|
||||
+ printf("%s: HIF Rx desc not initialized \n", __func__);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ rx_desc = g_rx_desc;
|
||||
+ bd_va = rx_desc->rxBase;
|
||||
+
|
||||
+ for (i=0; i < rx_desc->rxRingSize; i++) {
|
||||
+ bd_va->ctrl |= BD_CTRL_LAST_BD;
|
||||
bd_va++;
|
||||
}
|
||||
}
|
||||
|
||||
+
|
||||
/** HIF Rx Desc initialization function.
|
||||
*/
|
||||
static int hif_rx_desc_init(struct pfe *pfe)
|
||||
@@ -348,7 +382,11 @@ static int hif_rx_desc_init(struct pfe *pfe)
|
||||
|
||||
memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
|
||||
|
||||
+#if defined(PFE_LS1012A_RESET_WA)
|
||||
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
|
||||
+#else
|
||||
ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
|
||||
+#endif
|
||||
for (i=0; i < rx_desc->rxRingSize; i++) {
|
||||
bd_va->next = (u32 )(bd_pa + 1);
|
||||
bd_va->ctrl = ctrl;
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
|
||||
index 40ac095..40f2c39 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.c
|
||||
@@ -48,7 +48,7 @@ static void ls1012a_gemac_enable(void *gemac_base)
|
||||
writel(readl(gemac_base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
|
||||
}
|
||||
|
||||
-static void ls1012a_gemac_dsable(void *gemac_base)
|
||||
+static void ls1012a_gemac_disable(void *gemac_base)
|
||||
{
|
||||
writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
|
||||
}
|
||||
@@ -113,7 +113,7 @@ static void ls1012a_eth_halt(struct eth_device *edev)
|
||||
{
|
||||
struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)edev->priv;
|
||||
|
||||
- ls1012a_gemac_enable(priv->gem->gemac_base);
|
||||
+ ls1012a_gemac_disable(priv->gem->gemac_base);
|
||||
|
||||
gpi_disable(priv->gem->egpi_base);
|
||||
|
||||
@@ -216,14 +216,12 @@ static int ls1012a_eth_recv(struct eth_device *dev)
|
||||
dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
|
||||
if (phy_port != priv->gemac_port) {
|
||||
printf("Rx pkt not on expected port\n");
|
||||
- pfe_recv_ack();
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Pass the packet up to the protocol layers.
|
||||
net_process_received_packet((uchar *)pkt_buf, len);
|
||||
|
||||
- pfe_recv_ack();
|
||||
return 0;
|
||||
}
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,48 +0,0 @@ |
||||
From fe0ffa96c83e318d6b99fe31b5d121bdb05247f7 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Tue, 24 May 2016 14:52:59 +0530
|
||||
Subject: [PATCH 44/93] armv8: fsl-layerscape: Add support of GPIO structure
|
||||
|
||||
[context adjustment]
|
||||
|
||||
Layerscape supports GPIO registers to conrol GPIO singals.
|
||||
|
||||
Add support of GPIO structure to enable GPIO access.
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index a264f9a..58c7205 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -44,6 +44,7 @@
|
||||
#define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
|
||||
+#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
|
||||
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
|
||||
@@ -650,6 +651,15 @@ struct ccsr_cci400 {
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
|
||||
+typedef struct ccsr_gpio {
|
||||
+ u32 gpdir;
|
||||
+ u32 gpodr;
|
||||
+ u32 gpdat;
|
||||
+ u32 gpier;
|
||||
+ u32 gpimr;
|
||||
+ u32 gpicr;
|
||||
+} ccsr_gpio_t;
|
||||
+
|
||||
/* MMU 500 */
|
||||
#define SMMU_SCR0 (SMMU_BASE + 0x0)
|
||||
#define SMMU_SCR1 (SMMU_BASE + 0x4)
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,155 +0,0 @@ |
||||
From 691deae097b2583a4e9890307c684ce9f58aca78 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Tue, 24 May 2016 15:03:33 +0530
|
||||
Subject: [PATCH 45/93] board/freescale/ls1012afrdm: Add support of Ethernet
|
||||
|
||||
Add support of SGMII Ethernet present on FRDM board.
|
||||
Also add support of PHY reset.
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012afrdm/Makefile | 1 +
|
||||
board/freescale/ls1012afrdm/eth.c | 86 +++++++++++++++++++++++++++++
|
||||
board/freescale/ls1012afrdm/ls1012afrdm.c | 5 --
|
||||
include/configs/ls1012afrdm.h | 5 ++
|
||||
4 files changed, 92 insertions(+), 5 deletions(-)
|
||||
create mode 100644 board/freescale/ls1012afrdm/eth.c
|
||||
|
||||
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
|
||||
index dbfa2ce..1364f22 100644
|
||||
--- a/board/freescale/ls1012afrdm/Makefile
|
||||
+++ b/board/freescale/ls1012afrdm/Makefile
|
||||
@@ -5,3 +5,4 @@
|
||||
#
|
||||
|
||||
obj-y += ls1012afrdm.o
|
||||
+obj-y += eth.o
|
||||
diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
|
||||
new file mode 100644
|
||||
index 0000000..8ae3f45
|
||||
--- /dev/null
|
||||
+++ b/board/freescale/ls1012afrdm/eth.c
|
||||
@@ -0,0 +1,86 @@
|
||||
+/*
|
||||
+ * Copyright 2016 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <netdev.h>
|
||||
+#include <fm_eth.h>
|
||||
+#include <fsl_mdio.h>
|
||||
+#include <malloc.h>
|
||||
+#include <fsl_dtsec.h>
|
||||
+#include <asm/arch/soc.h>
|
||||
+#include <asm/arch-fsl-layerscape/config.h>
|
||||
+#include <asm/arch/fsl_serdes.h>
|
||||
+
|
||||
+#include "../../../drivers/net/pfe_eth/pfe_eth.h"
|
||||
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
|
||||
+
|
||||
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
||||
+
|
||||
+#define MASK_ETH_PHY_RST 0x00000100
|
||||
+
|
||||
+void reset_phy(void)
|
||||
+{
|
||||
+ unsigned int val;
|
||||
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_GPIO1_ADDR);
|
||||
+
|
||||
+ setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
|
||||
+
|
||||
+ val = in_be32(&pgpio->gpdat);
|
||||
+ setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ val = in_be32(&pgpio->gpdat);
|
||||
+ setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
|
||||
+ mdelay(50);
|
||||
+}
|
||||
+
|
||||
+int board_eth_init(bd_t *bis)
|
||||
+{
|
||||
+#ifdef CONFIG_FSL_PPFE
|
||||
+ struct mii_dev *bus;
|
||||
+ struct mdio_info mac1_mdio_info;
|
||||
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
+
|
||||
+
|
||||
+ /*TODO Following config should be done for all boards, where is the right place to put this */
|
||||
+ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
|
||||
+ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
|
||||
+
|
||||
+ /*CCI-400 QoS settings for PFE */
|
||||
+ out_be32(&scfg->wr_qos1, 0x0ff00000);
|
||||
+ out_be32(&scfg->rd_qos1, 0x0ff00000);
|
||||
+
|
||||
+ /* Set RGMII into 1G + Full duplex mode */
|
||||
+ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
|
||||
+
|
||||
+
|
||||
+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
|
||||
+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
|
||||
+
|
||||
+ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
|
||||
+ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
|
||||
+
|
||||
+ bus = ls1012a_mdio_init(&mac1_mdio_info);
|
||||
+ if(!bus)
|
||||
+ {
|
||||
+ printf("Failed to register mdio \n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ /*MAC1 */
|
||||
+ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
|
||||
+ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
|
||||
+
|
||||
+ /*MAC2 */
|
||||
+ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
|
||||
+ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
|
||||
+
|
||||
+
|
||||
+ cpu_eth_init(bis);
|
||||
+#endif
|
||||
+ return pci_eth_init(bis);
|
||||
+}
|
||||
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
index 6be8951..6856250 100644
|
||||
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
@@ -133,11 +133,6 @@ int dram_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
-int board_eth_init(bd_t *bis)
|
||||
-{
|
||||
- return pci_eth_init(bis);
|
||||
-}
|
||||
-
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
fsl_lsch2_early_init_f();
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 3231ab7..5e619c1 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -18,8 +18,13 @@
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
+#ifdef CONFIG_FSL_PPFE
|
||||
+#define EMAC1_PHY_ADDR 0x2
|
||||
+#define EMAC2_PHY_ADDR 0x1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_REALTEK
|
||||
+#define CONFIG_RESET_PHY_R
|
||||
+#endif
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,29 +0,0 @@ |
||||
From ff5e4bb56636eb807f653a0e1ce5c7c721543e01 Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Wed, 25 May 2016 17:57:25 +0530
|
||||
Subject: [PATCH 46/93] Correcting address for PFE Driver
|
||||
|
||||
[context adjustment]
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index 58c7205..a7bc2a4 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -44,7 +44,7 @@
|
||||
#define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
|
||||
-#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
|
||||
+#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x1300000)
|
||||
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,61 +0,0 @@ |
||||
From 61bb1dceefdb4c08ff69e7e40a766a404421206f Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Fri, 27 May 2016 13:16:43 +0530
|
||||
Subject: [PATCH 47/93] Enable second SGMII 1G interface
|
||||
|
||||
Enable second SGMII 1G interface on LS1012A Freedom Board
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012afrdm/eth.c | 14 ++++++++++++++
|
||||
drivers/net/pfe_eth/pfe_eth.c | 2 +-
|
||||
2 files changed, 15 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
|
||||
index 8ae3f45..90ed66b 100644
|
||||
--- a/board/freescale/ls1012afrdm/eth.c
|
||||
+++ b/board/freescale/ls1012afrdm/eth.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <asm/arch-fsl-layerscape/immap_lsch2.h>
|
||||
|
||||
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
||||
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
|
||||
|
||||
#define MASK_ETH_PHY_RST 0x00000100
|
||||
|
||||
@@ -71,6 +72,19 @@ int board_eth_init(bd_t *bis)
|
||||
return -1;
|
||||
}
|
||||
|
||||
+ /*We don't really need this MDIO bus,
|
||||
+ * this is called just to initialize EMAC2 MDIO interface*/
|
||||
+ mac1_mdio_info.reg_base = (void *)0x04220000; /*EMAC2_BASE_ADDR*/
|
||||
+ mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
|
||||
+
|
||||
+ bus = ls1012a_mdio_init(&mac1_mdio_info);
|
||||
+ if(!bus)
|
||||
+ {
|
||||
+ printf("Failed to register mdio \n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+
|
||||
/*MAC1 */
|
||||
ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
|
||||
ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
|
||||
index 40f2c39..4aa318d 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.c
|
||||
@@ -348,7 +348,7 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
|
||||
|
||||
printf("%s %d\n", __func__, priv->gemac_port);
|
||||
/* PCS configuration done with corresponding GEMAC */
|
||||
- bus.priv = priv->gem->gemac_base;
|
||||
+ bus.priv = gem_info[priv->gemac_port].gemac_base;
|
||||
|
||||
ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
|
||||
ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,44 +0,0 @@ |
||||
From a75fda9a1a7d635d1714df52068cc9fb7988e2c7 Mon Sep 17 00:00:00 2001
|
||||
From: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Date: Fri, 3 Jun 2016 11:40:09 +0800
|
||||
Subject: [PATCH 48/93] armv8: ls1012a: enable sdhc2 support
|
||||
|
||||
A previous patch shifting board specific configurations missed
|
||||
the sdhc2 support. This patch is to fix it.
|
||||
|
||||
Fixes: df5f76d71e30 ("Shift board specific configurations")
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
include/configs/ls1012aqds.h | 2 ++
|
||||
include/configs/ls1012ardb.h | 2 ++
|
||||
2 files changed, 4 insertions(+)
|
||||
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index 1fa7b6f..cc8e0fc 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -30,6 +30,8 @@
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
+#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
|
||||
+#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index 23722e0..2eee84a 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -64,6 +64,8 @@
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
+#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
|
||||
+#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,327 +0,0 @@ |
||||
From 1b9cf577511123dd05e1d3b1fe7fd5db43b6097f Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Wed, 25 May 2016 13:40:13 +0530
|
||||
Subject: [PATCH 49/93] DNCPE-296 PFE reset woraround fix
|
||||
|
||||
- Linux driver depends on U-boot TMU initialization,
|
||||
but U-boot tmu initialization is not as expected by Linux driver.
|
||||
- Align U-boot TMU initialization with Linux driver
|
||||
- LLM base address in DDR changed to match with Linux driver expectation.
|
||||
- Remove unwanted pfe_mod.h
|
||||
- Start PFE/network at bootup time.
|
||||
---
|
||||
common/cmd_pfe_commands.c | 9 +-
|
||||
drivers/net/pfe_eth/pfe.c | 16 ++--
|
||||
drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 7 ++
|
||||
drivers/net/pfe_eth/pfe_eth.h | 9 +-
|
||||
drivers/net/pfe_eth/pfe_mod.h | 140 --------------------------------
|
||||
include/configs/ls1012a_common.h | 1 -
|
||||
6 files changed, 24 insertions(+), 158 deletions(-)
|
||||
delete mode 100644 drivers/net/pfe_eth/pfe_mod.h
|
||||
|
||||
diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
|
||||
index 0e22097..ca479d7 100644
|
||||
--- a/common/cmd_pfe_commands.c
|
||||
+++ b/common/cmd_pfe_commands.c
|
||||
@@ -932,7 +932,7 @@ static void send_dummy_pkt_to_hif(void)
|
||||
/*Allocate BMU2 buffer */
|
||||
buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
|
||||
|
||||
- printf("Sending a dummy pkt to HIF %x\n", buf);
|
||||
+ debug("Sending a dummy pkt to HIF %x\n", buf);
|
||||
buf += 0x80;
|
||||
memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
|
||||
/*Write length and pkt to TMU*/
|
||||
@@ -945,14 +945,13 @@ static void pfe_command_stop(int argc, char * const argv[])
|
||||
{
|
||||
int id;
|
||||
u32 rx_status;
|
||||
- printf("Stopping PFE \n");
|
||||
+ printf("Stopping PFE... \n");
|
||||
|
||||
/*Mark all descriptors as LAST_BD */
|
||||
hif_rx_desc_disable();
|
||||
|
||||
/*If HIF Rx BDP is busy send a dummy packet */
|
||||
rx_status = readl(HIF_RX_STATUS);
|
||||
- printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
|
||||
if(rx_status & BDP_CSR_RX_DMA_ACTV)
|
||||
send_dummy_pkt_to_hif();
|
||||
udelay(10);
|
||||
@@ -964,12 +963,10 @@ static void pfe_command_stop(int argc, char * const argv[])
|
||||
|
||||
for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
|
||||
{
|
||||
- printf("Stop %d\n", id);
|
||||
/*Inform PE to stop */
|
||||
pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
|
||||
udelay(10);
|
||||
|
||||
- printf("Reading %d\n", id);
|
||||
/*Read status */
|
||||
if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
|
||||
printf("Failed to stop PE%d\n", id);
|
||||
@@ -979,12 +976,10 @@ static void pfe_command_stop(int argc, char * const argv[])
|
||||
{
|
||||
if(id == TMU2_ID) continue;
|
||||
|
||||
- printf("Stop %d\n", id);
|
||||
/*Inform PE to stop */
|
||||
pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
|
||||
udelay(10);
|
||||
|
||||
- printf("Reading %d\n", id);
|
||||
/*Read status */
|
||||
if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
|
||||
printf("Failed to stop PE%d\n", id);
|
||||
diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
|
||||
index 3b5570a..2c31cad 100644
|
||||
--- a/drivers/net/pfe_eth/pfe.c
|
||||
+++ b/drivers/net/pfe_eth/pfe.c
|
||||
@@ -1489,17 +1489,16 @@ void tmu_init(TMU_CFG *cfg)
|
||||
writel(0x3FF, TMU_TDQ2_SCH_CTRL);
|
||||
#endif
|
||||
writel(0x3FF, TMU_TDQ3_SCH_CTRL);
|
||||
-
|
||||
-
|
||||
+
|
||||
if (PLL_CLK_EN == 0)
|
||||
writel(0x0, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
|
||||
else
|
||||
writel(0x1, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
|
||||
|
||||
- //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
|
||||
+ debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
|
||||
writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
|
||||
-
|
||||
- //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
|
||||
+
|
||||
+ debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
|
||||
writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
|
||||
writel(5, TMU_TDQ_IIFG_CFG);
|
||||
writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
|
||||
@@ -1531,7 +1530,12 @@ void tmu_init(TMU_CFG *cfg)
|
||||
u32 qmax;
|
||||
writel((phyno << 8) | q, TMU_TEQ_CTRL);
|
||||
writel(1 << 22, TMU_TEQ_QCFG);
|
||||
- qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
|
||||
+
|
||||
+ if (phyno == 3)
|
||||
+ qmax = DEFAULT_TMU3_QDEPTH;
|
||||
+ else
|
||||
+ qmax = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
|
||||
+
|
||||
writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
|
||||
writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
|
||||
}
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
|
||||
index cbcbb1f..64fad04 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
|
||||
@@ -93,10 +93,17 @@
|
||||
#define MEM_INIT_DONE (1 << 7)
|
||||
#define LLM_INIT (1 << 8)
|
||||
#define LLM_INIT_DONE (1 << 9)
|
||||
+#define ECC_MEM_INIT_DONE (1<<10)
|
||||
|
||||
typedef struct {
|
||||
u32 llm_base_addr;
|
||||
u32 llm_queue_len;
|
||||
} TMU_CFG;
|
||||
|
||||
+/* Not HW related for pfe_ctrl / pfe common defines */
|
||||
+#define DEFAULT_MAX_QDEPTH 80
|
||||
+#define DEFAULT_Q0_QDEPTH 511 //We keep one large queue for host tx qos
|
||||
+#define DEFAULT_TMU3_QDEPTH 127
|
||||
+
|
||||
+
|
||||
#endif /* _TMU_CSR_H_ */
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
|
||||
index dfcc00e..c16b8c0 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.h
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.h
|
||||
@@ -39,11 +39,8 @@
|
||||
#define BMU2_BUF_COUNT (3 * SZ_1K)
|
||||
#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
|
||||
|
||||
-#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
|
||||
-#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
|
||||
-#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
|
||||
|
||||
-#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
|
||||
+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
|
||||
#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
|
||||
#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
|
||||
#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
|
||||
@@ -72,6 +69,10 @@
|
||||
#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
|
||||
#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
|
||||
|
||||
+#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
|
||||
+#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
|
||||
+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
|
||||
+
|
||||
//#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
|
||||
#define ROUTE_TABLE_BASEADDR 0x800000
|
||||
#define ROUTE_TABLE_HASH_BITS_MAX 15 /**< 32K entries */
|
||||
diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
|
||||
deleted file mode 100644
|
||||
index 9436b72..0000000
|
||||
--- a/drivers/net/pfe_eth/pfe_mod.h
|
||||
+++ /dev/null
|
||||
@@ -1,140 +0,0 @@
|
||||
-/*
|
||||
- * (C) Copyright 2011
|
||||
- * Author : Mindspeed Technologes
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- * */
|
||||
-
|
||||
-
|
||||
-#ifndef _PFE_MOD_H_
|
||||
-#define _PFE_MOD_H_
|
||||
-
|
||||
-#include <linux/device.h>
|
||||
-
|
||||
-#include "pfe/pfe.h"
|
||||
-#include "pfe/cbus.h"
|
||||
-#include "pfe/cbus/bmu.h"
|
||||
-
|
||||
-#include "pfe_driver.h"
|
||||
-
|
||||
-struct pfe;
|
||||
-
|
||||
-
|
||||
-struct pfe {
|
||||
- unsigned long ddr_phys_baseaddr;
|
||||
- void *ddr_baseaddr;
|
||||
- void *cbus_baseaddr;
|
||||
- void *apb_baseaddr;
|
||||
- void *iram_baseaddr;
|
||||
- int hif_irq;
|
||||
- struct device *dev;
|
||||
- struct pci_dev *pdev;
|
||||
-
|
||||
-#if 0
|
||||
- struct pfe_ctrl ctrl;
|
||||
- struct pfe_hif hif;
|
||||
- struct pfe_eth eth;
|
||||
-#endif
|
||||
-};
|
||||
-
|
||||
-extern struct pfe *pfe;
|
||||
-
|
||||
-int pfe_probe(struct pfe *pfe);
|
||||
-int pfe_remove(struct pfe *pfe);
|
||||
-
|
||||
-#ifndef SZ_1K
|
||||
-#define SZ_1K 1024
|
||||
-#endif
|
||||
-
|
||||
-#ifndef SZ_1M
|
||||
-#define SZ_1M (1024 * 1024)
|
||||
-#endif
|
||||
-
|
||||
-/* DDR Mapping */
|
||||
-#if !defined(CONFIG_PLATFORM_PCI)
|
||||
-#define UTIL_CODE_BASEADDR 0
|
||||
-#define UTIL_CODE_SIZE (128 * SZ_1K)
|
||||
-#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
|
||||
-#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
|
||||
-#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
|
||||
-#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
|
||||
-#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
|
||||
-#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
|
||||
-#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
|
||||
-#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
|
||||
-#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
|
||||
-#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
|
||||
-#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
|
||||
-#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
|
||||
-#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
|
||||
-#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
|
||||
-#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
|
||||
-
|
||||
-#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
|
||||
-#error DDR mapping above 12MiB
|
||||
-#endif
|
||||
-
|
||||
-#else
|
||||
-
|
||||
-#define UTIL_CODE_BASEADDR 0
|
||||
-#if defined(CONFIG_UTIL_PE_DISABLED)
|
||||
-#define UTIL_CODE_SIZE (0 * SZ_1K)
|
||||
-#else
|
||||
-#define UTIL_CODE_SIZE (8 * SZ_1K)
|
||||
-#endif
|
||||
-#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
|
||||
-#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
|
||||
-#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
|
||||
-#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
|
||||
-#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
|
||||
-#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
|
||||
-#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
|
||||
-#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
|
||||
-#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
|
||||
-#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
|
||||
-#define BMU2_BUF_COUNT 8
|
||||
-#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
|
||||
-#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
|
||||
-#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
|
||||
-#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
|
||||
-#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
|
||||
-#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
|
||||
-#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
|
||||
-#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
|
||||
-#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
|
||||
-#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
|
||||
-#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
|
||||
-#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
|
||||
-#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
|
||||
-#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
|
||||
-
|
||||
-#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
|
||||
-#error DDR mapping above 64KiB
|
||||
-#endif
|
||||
-
|
||||
-#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
|
||||
-#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
|
||||
-#endif
|
||||
-
|
||||
-/* LMEM Mapping */
|
||||
-#define BMU1_LMEM_BASEADDR 0
|
||||
-#define BMU1_BUF_COUNT 256
|
||||
-#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
|
||||
-
|
||||
-#endif /* _PFE_MOD_H */
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 3c4ab6c..57fc057 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -113,7 +113,6 @@
|
||||
#define CONFIG_FSL_PPFE
|
||||
|
||||
#ifdef CONFIG_FSL_PPFE
|
||||
-#define CONFIG_CMD_PFE_START
|
||||
#define CONFIG_CMD_PFE_COMMANDS
|
||||
#define CONFIG_UTIL_PE_DISABLED
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,54 +0,0 @@ |
||||
From 101bee08b8441f279df657d4a45868de3f976c0c Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Thu, 26 May 2016 15:58:48 +0530
|
||||
Subject: [PATCH 50/93] DNCPE-138 Rest external PHYs before driver starts
|
||||
|
||||
- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started.
|
||||
- Call reset_phy() before driver initialization.
|
||||
- Update bootcmd to stop pfe before kernel starts.
|
||||
---
|
||||
board/freescale/ls1012ardb/eth.c | 1 +
|
||||
include/configs/ls1012a_common.h | 2 +-
|
||||
include/configs/ls1012ardb.h | 1 -
|
||||
3 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
|
||||
index 24fdd83..638db95 100644
|
||||
--- a/board/freescale/ls1012ardb/eth.c
|
||||
+++ b/board/freescale/ls1012ardb/eth.c
|
||||
@@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis)
|
||||
struct mdio_info mac1_mdio_info;
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
|
||||
+ reset_phy();
|
||||
|
||||
/*TODO Following config should be done for all boards, where is the right place to put this */
|
||||
out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 57fc057..2895e7a 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -152,7 +152,7 @@
|
||||
#else
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
|
||||
"earlycon=uart8250,mmio,0x21c0500"
|
||||
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
|
||||
+#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
|
||||
"$kernel_start $kernel_size && "\
|
||||
"bootm $kernel_load"
|
||||
#endif
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index 2eee84a..e94df74 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -24,7 +24,6 @@
|
||||
#define EMAC2_PHY_ADDR 0x1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_REALTEK
|
||||
-#define CONFIG_RESET_PHY_R
|
||||
#endif
|
||||
|
||||
/*
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,283 +0,0 @@ |
||||
From 4332e5748301df5b608f894e451999f873bda307 Mon Sep 17 00:00:00 2001
|
||||
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
|
||||
Date: Wed, 1 Jun 2016 05:18:38 +0530
|
||||
Subject: [PATCH 51/93] PPFE warnings Fix
|
||||
|
||||
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
|
||||
---
|
||||
Makefile | 1 +
|
||||
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 +
|
||||
board/freescale/ls1012aqds/eth.c | 4 ++--
|
||||
board/freescale/ls1012ardb/eth.c | 1 +
|
||||
common/cmd_pfe_commands.c | 7 +++++--
|
||||
drivers/net/pfe_eth/pfe.c | 7 ++++---
|
||||
drivers/net/pfe_eth/pfe/pfe.h | 2 +-
|
||||
drivers/net/pfe_eth/pfe_driver.c | 8 ++++----
|
||||
drivers/net/pfe_eth/pfe_eth.c | 7 +------
|
||||
drivers/net/pfe_eth/pfe_eth.h | 6 +++++-
|
||||
drivers/net/pfe_eth/pfe_firmware.c | 2 +-
|
||||
11 files changed, 26 insertions(+), 20 deletions(-)
|
||||
|
||||
diff --git a/Makefile b/Makefile
|
||||
index 100de92..1c2818c 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -612,6 +612,7 @@ UBOOTINCLUDE := \
|
||||
$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
|
||||
-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
|
||||
-I$(srctree)/arch/$(ARCH)/include \
|
||||
+ -I$(srctree)/drivers/net/pfe_eth \
|
||||
-include $(srctree)/include/linux/kconfig.h
|
||||
|
||||
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
|
||||
index 8f59577..bfd7078 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
|
||||
@@ -20,6 +20,7 @@
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_debug_server.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
+#include <pfe_eth.h>
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
|
||||
index 1bd7c9d..6fbbdbe 100644
|
||||
--- a/board/freescale/ls1012aqds/eth.c
|
||||
+++ b/board/freescale/ls1012aqds/eth.c
|
||||
@@ -27,8 +27,6 @@
|
||||
|
||||
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
||||
|
||||
-static int mdio_mux[NUM_FM_PORTS];
|
||||
-
|
||||
static const char * const mdio_names[] = {
|
||||
"NULL",
|
||||
"LS1012AQDS_MDIO_RGMII",
|
||||
@@ -85,6 +83,8 @@ static int ls1012aqds_mdio_reset(struct mii_dev *bus)
|
||||
|
||||
if(priv->realbus->reset)
|
||||
return priv->realbus->reset(priv->realbus);
|
||||
+ else
|
||||
+ return -1;
|
||||
}
|
||||
|
||||
static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
|
||||
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
|
||||
index 638db95..7b0e450 100644
|
||||
--- a/board/freescale/ls1012ardb/eth.c
|
||||
+++ b/board/freescale/ls1012ardb/eth.c
|
||||
@@ -17,6 +17,7 @@
|
||||
|
||||
#include "../../../drivers/net/pfe_eth/pfe_eth.h"
|
||||
#include <asm/arch-fsl-layerscape/immap_lsch2.h>
|
||||
+#include <i2c.h>
|
||||
|
||||
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
||||
|
||||
diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
|
||||
index ca479d7..84999a6 100644
|
||||
--- a/common/cmd_pfe_commands.c
|
||||
+++ b/common/cmd_pfe_commands.c
|
||||
@@ -602,7 +602,6 @@ void bmu(int id, void *base)
|
||||
static void pfe_pe_status(int argc, char * const argv[])
|
||||
{
|
||||
int do_clear = 0;
|
||||
- int j;
|
||||
u32 id;
|
||||
u32 dmem_addr;
|
||||
u32 cpu_state;
|
||||
@@ -612,9 +611,11 @@ static void pfe_pe_status(int argc, char * const argv[])
|
||||
u32 drop;
|
||||
char statebuf[5];
|
||||
u32 class_debug_reg = 0;
|
||||
+#ifdef CONFIG_PFE_WARN_WA
|
||||
u32 debug_indicator;
|
||||
u32 debug[16];
|
||||
-
|
||||
+ int j;
|
||||
+#endif
|
||||
if (argc == 4 && strcmp(argv[3], "clear") == 0)
|
||||
do_clear = 1;
|
||||
|
||||
@@ -684,6 +685,7 @@ static void pfe_pe_status(int argc, char * const argv[])
|
||||
statebuf, cpu_to_be32(activity_counter),
|
||||
cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
|
||||
}
|
||||
+#ifdef CONFIG_PFE_WARN_WA
|
||||
debug_indicator = pe_dmem_read(id, dmem_addr, 4);
|
||||
dmem_addr += 4;
|
||||
if (debug_indicator == cpu_to_be32('DBUG'))
|
||||
@@ -705,6 +707,7 @@ static void pfe_pe_status(int argc, char * const argv[])
|
||||
printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
|
||||
}
|
||||
}
|
||||
+#endif
|
||||
}
|
||||
|
||||
}
|
||||
diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
|
||||
index 2c31cad..94cfe4e 100644
|
||||
--- a/drivers/net/pfe_eth/pfe.c
|
||||
+++ b/drivers/net/pfe_eth/pfe.c
|
||||
@@ -368,6 +368,7 @@ void pe_lmem_write(u32 *src, u32 len, u32 offset)
|
||||
class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
|
||||
}
|
||||
|
||||
+#if !defined(CONFIG_UTIL_PE_DISABLED)
|
||||
/** Writes UTIL program memory (DDR) from the host.
|
||||
*
|
||||
* @param[in] addr Address to write (virtual, must be aligned on size)
|
||||
@@ -413,7 +414,7 @@ static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
|
||||
if (len & 0x2)
|
||||
util_pmem_write(*(u16 *)src, dst, len & 0x2);
|
||||
}
|
||||
-
|
||||
+#endif
|
||||
|
||||
/** Loads an elf section into pmem
|
||||
* Code needs to be at least 16bit aligned and only PROGBITS sections are supported
|
||||
@@ -581,7 +582,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
|
||||
return -1;
|
||||
}
|
||||
|
||||
- memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
|
||||
+ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -620,7 +621,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
|
||||
}
|
||||
else
|
||||
{
|
||||
- memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
|
||||
+ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
|
||||
}
|
||||
|
||||
break;
|
||||
diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
|
||||
index 6994a20..9445155 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/pfe.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/pfe.h
|
||||
@@ -50,7 +50,7 @@ extern void *ddr_base_addr;
|
||||
#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
|
||||
|
||||
/* Host<->PFE Mapping */
|
||||
-#define DDR_PFE_TO_VIRT(p) ((p ) + 0x80000000)
|
||||
+#define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p ) + 0x80000000))
|
||||
#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
|
||||
#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
|
||||
index b06a352..2f4c385 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_driver.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_driver.c
|
||||
@@ -87,7 +87,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
}
|
||||
#endif
|
||||
|
||||
- *pkt_ptr = (unsigned int )(hif_header + 1);
|
||||
+ *pkt_ptr = (unsigned long)(hif_header + 1);
|
||||
*phy_port = hif_header->port_no;
|
||||
len -= sizeof(struct hif_header_s);
|
||||
|
||||
@@ -174,7 +174,7 @@ int pfe_send(int phy_port, void *data, int length)
|
||||
length = MIN_PKT_SIZE;
|
||||
}
|
||||
|
||||
- tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
|
||||
+ tx_buf_va = (void *)DDR_PFE_TO_VIRT(bd->data);
|
||||
dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
|
||||
|
||||
/* Fill the gemac/phy port number to send this packet out */
|
||||
@@ -388,7 +388,7 @@ static int hif_rx_desc_init(struct pfe *pfe)
|
||||
ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
|
||||
#endif
|
||||
for (i=0; i < rx_desc->rxRingSize; i++) {
|
||||
- bd_va->next = (u32 )(bd_pa + 1);
|
||||
+ bd_va->next = (unsigned long)(bd_pa + 1);
|
||||
bd_va->ctrl = ctrl;
|
||||
bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
|
||||
// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
|
||||
@@ -476,7 +476,7 @@ static int hif_tx_desc_init(struct pfe *pfe)
|
||||
tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
|
||||
|
||||
for (i=0; i < tx_desc->txRingSize; i++) {
|
||||
- bd_va->next = (u32 )(bd_pa + 1);
|
||||
+ bd_va->next = (unsigned long)(bd_pa + 1);
|
||||
bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
|
||||
// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
|
||||
// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
|
||||
index 4aa318d..4a935ca 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.c
|
||||
@@ -53,10 +53,6 @@ static void ls1012a_gemac_disable(void *gemac_base)
|
||||
writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
|
||||
}
|
||||
|
||||
-static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
|
||||
-{
|
||||
-}
|
||||
-
|
||||
static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
|
||||
{
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
@@ -125,7 +121,6 @@ static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
|
||||
struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
|
||||
struct gemac_s *gem = priv->gem;
|
||||
int speed;
|
||||
- int tmp;
|
||||
|
||||
/* set ethernet mac address */
|
||||
ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
|
||||
@@ -220,7 +215,7 @@ static int ls1012a_eth_recv(struct eth_device *dev)
|
||||
}
|
||||
|
||||
// Pass the packet up to the protocol layers.
|
||||
- net_process_received_packet((uchar *)pkt_buf, len);
|
||||
+ net_process_received_packet((void *)(long int)pkt_buf, len);
|
||||
|
||||
return 0;
|
||||
}
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
|
||||
index c16b8c0..af6191d 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.h
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.h
|
||||
@@ -26,6 +26,7 @@
|
||||
|
||||
|
||||
#include "pfe_driver.h"
|
||||
+#include <phy.h>
|
||||
|
||||
#ifndef SZ_1K
|
||||
#define SZ_1K 1024
|
||||
@@ -151,7 +152,10 @@ struct firmware {
|
||||
|
||||
int pfe_probe(struct pfe *pfe);
|
||||
int pfe_remove(struct pfe *pfe);
|
||||
-
|
||||
+struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info);
|
||||
+void ls1012a_set_mdio(int dev_id, struct mii_dev *bus);
|
||||
+void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
|
||||
+int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
|
||||
|
||||
//#define dprint(fmt, arg...) printf(fmt, ##arg)
|
||||
#define dprint(fmt, arg...)
|
||||
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
|
||||
index 165eb3c..5957afd 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_firmware.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_firmware.c
|
||||
@@ -45,7 +45,7 @@ int pfe_load_elf(int pe_mask, const struct firmware *fw)
|
||||
printf("%s: no of sections: %d\n", __func__, sections);
|
||||
|
||||
/* Some sanity checks */
|
||||
- if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
|
||||
+ if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
|
||||
{
|
||||
printf("%s: incorrect elf magic number\n", __func__);
|
||||
return -1;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,688 +0,0 @@ |
||||
From e6ab05ee921fe2c8ae2dabdd5c1f27e2ff2446cb Mon Sep 17 00:00:00 2001
|
||||
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
|
||||
Date: Mon, 13 Jun 2016 07:37:52 +0530
|
||||
Subject: [PATCH 52/93] Add Freescale Copyright in PPFE driver
|
||||
|
||||
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
|
||||
---
|
||||
board/freescale/ls1012ardb/eth.c | 2 +-
|
||||
common/cmd_gemac_stat.c | 25 ++++---------------------
|
||||
common/cmd_pfe_commands.c | 25 ++++---------------------
|
||||
drivers/net/pfe_eth/Makefile | 4 ++++
|
||||
drivers/net/pfe_eth/hal.h | 26 ++++----------------------
|
||||
drivers/net/pfe_eth/pfe.c | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/bmu.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/class_csr.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/emac.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/gpi.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/gpt.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/hif.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/cbus/util_csr.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/class.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/class/ccu.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/class/efet.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/class/mac_hash.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/class/perg.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/class/vlan_hash.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/gpt.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/pe.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/pfe.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/tmu.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/tmu/phy_queue.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/tmu/sched.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/tmu/shaper.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/uart.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/util/eape.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/util/efet.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe/util/inq.h | 5 +++++
|
||||
drivers/net/pfe_eth/pfe_driver.c | 27 ++++-----------------------
|
||||
drivers/net/pfe_eth/pfe_driver.h | 26 ++++----------------------
|
||||
drivers/net/pfe_eth/pfe_eth.c | 5 +++++
|
||||
drivers/net/pfe_eth/pfe_eth.h | 26 ++++----------------------
|
||||
drivers/net/pfe_eth/pfe_firmware.c | 6 +++++-
|
||||
drivers/net/pfe_eth/pfe_firmware.h | 6 +++++-
|
||||
39 files changed, 184 insertions(+), 134 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
|
||||
index 7b0e450..34ba56d 100644
|
||||
--- a/board/freescale/ls1012ardb/eth.c
|
||||
+++ b/board/freescale/ls1012ardb/eth.c
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
- * SPDX-License-Identifier: GPL-2.0+
|
||||
+ * SPDX-License-Identifier:GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
|
||||
index 49bb1aa..fb621a2 100644
|
||||
--- a/common/cmd_gemac_stat.c
|
||||
+++ b/common/cmd_gemac_stat.c
|
||||
@@ -1,25 +1,8 @@
|
||||
/*
|
||||
- * (C) Copyright 2003
|
||||
- * Author : Laurent Brando (Mindspeed Technologies)
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- */
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
|
||||
index 84999a6..92917e0 100644
|
||||
--- a/common/cmd_pfe_commands.c
|
||||
+++ b/common/cmd_pfe_commands.c
|
||||
@@ -1,25 +1,8 @@
|
||||
/*
|
||||
- * (C) Copyright 2012
|
||||
- * Author : Bill Westland (Mindspeed Technologies)
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- */
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
|
||||
index 1af837d..bc45d8f 100644
|
||||
--- a/drivers/net/pfe_eth/Makefile
|
||||
+++ b/drivers/net/pfe_eth/Makefile
|
||||
@@ -1 +1,5 @@
|
||||
+# Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+#
|
||||
+# SPDX-License-Identifier:GPL-2.0+
|
||||
+
|
||||
obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
|
||||
diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
|
||||
index e795fe6..ff510ac 100644
|
||||
--- a/drivers/net/pfe_eth/hal.h
|
||||
+++ b/drivers/net/pfe_eth/hal.h
|
||||
@@ -1,26 +1,8 @@
|
||||
/*
|
||||
- * (C) Copyright 2011
|
||||
- * Author : Mindspeed Technologes
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- * */
|
||||
-
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _HAL_H_
|
||||
#define _HAL_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
|
||||
index 94cfe4e..68cf23a 100644
|
||||
--- a/drivers/net/pfe_eth/pfe.c
|
||||
+++ b/drivers/net/pfe_eth/pfe.c
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#include "hal.h"
|
||||
#include "pfe/pfe.h"
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus.h b/drivers/net/pfe_eth/pfe/cbus.h
|
||||
index 778fe45..d46a765 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _CBUS_H_
|
||||
#define _CBUS_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/bmu.h b/drivers/net/pfe_eth/pfe/cbus/bmu.h
|
||||
index f3e5e6d..fd37570 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/bmu.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/bmu.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _BMU_H_
|
||||
#define _BMU_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/class_csr.h b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
|
||||
index f3151ec..4c2c3fa 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/class_csr.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _CLASS_CSR_H_
|
||||
#define _CLASS_CSR_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/emac.h b/drivers/net/pfe_eth/pfe/cbus/emac.h
|
||||
index 1f308ce..aead064 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/emac.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/emac.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _EMAC_H_
|
||||
#define _EMAC_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/gpi.h b/drivers/net/pfe_eth/pfe/cbus/gpi.h
|
||||
index d2d165f..7792d6c 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/gpi.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/gpi.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _GPI_H_
|
||||
#define _GPI_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/gpt.h b/drivers/net/pfe_eth/pfe/cbus/gpt.h
|
||||
index f8c114b..0ec5fdc 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/gpt.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/gpt.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _CBUS_GPT_H_
|
||||
#define _CBUS_GPT_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
|
||||
index 2329faa..45bc0b2 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/hif.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _HIF_H_
|
||||
#define _HIF_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
|
||||
index 93cb946..55ddc8c 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _HIF_NOCPY_H_
|
||||
#define _HIF_NOCPY_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
|
||||
index 64fad04..058874e 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _TMU_CSR_H_
|
||||
#define _TMU_CSR_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/cbus/util_csr.h b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
|
||||
index d67e849..14079db 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/cbus/util_csr.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _UTIL_CSR_H_
|
||||
#define _UTIL_CSR_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/class.h b/drivers/net/pfe_eth/pfe/class.h
|
||||
index 33ad826..87b1399 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/class.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/class.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _CLASS_H_
|
||||
#define _CLASS_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/class/ccu.h b/drivers/net/pfe_eth/pfe/class/ccu.h
|
||||
index 2c43d97..605ac16 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/class/ccu.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/class/ccu.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _CCU_H_
|
||||
#define _CCU_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/class/efet.h b/drivers/net/pfe_eth/pfe/class/efet.h
|
||||
index 4f3cc25..7ef2978 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/class/efet.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/class/efet.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _CLASS_EFET_H_
|
||||
#define _CLASS_EFET_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/class/mac_hash.h b/drivers/net/pfe_eth/pfe/class/mac_hash.h
|
||||
index 68023b4..ca24ca5 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/class/mac_hash.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/class/mac_hash.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _MAC_HASH_H_
|
||||
#define _MAC_HASH_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/class/perg.h b/drivers/net/pfe_eth/pfe/class/perg.h
|
||||
index 7297171..dbb5a3b 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/class/perg.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/class/perg.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _PERG_H_
|
||||
#define _PERG_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/class/vlan_hash.h b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
|
||||
index a54ac19..cdad97c 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/class/vlan_hash.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _VLAN_HASH_H_
|
||||
#define _VLAN_HASH_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/gpt.h b/drivers/net/pfe_eth/pfe/gpt.h
|
||||
index d820277..6fce042 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/gpt.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/gpt.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _GPT_H_
|
||||
#define _GPT_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/pe.h b/drivers/net/pfe_eth/pfe/pe.h
|
||||
index a3838f5..ac8cbf2 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/pe.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/pe.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _PE_H_
|
||||
#define _PE_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
|
||||
index 9445155..ac1ecb8 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/pfe.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/pfe.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _PFE_H_
|
||||
#define _PFE_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/tmu.h b/drivers/net/pfe_eth/pfe/tmu.h
|
||||
index 12eaf12..dd697be 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/tmu.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/tmu.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _TMU_H_
|
||||
#define _TMU_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
|
||||
index 9eef9a9..b9a0925 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _PHY_QUEUE_H_
|
||||
#define _PHY_QUEUE_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/tmu/sched.h b/drivers/net/pfe_eth/pfe/tmu/sched.h
|
||||
index 0c741cc..954dc8f 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/tmu/sched.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/tmu/sched.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _SCHED_H_
|
||||
#define _SCHED_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/tmu/shaper.h b/drivers/net/pfe_eth/pfe/tmu/shaper.h
|
||||
index 76315f3..81c367d 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/tmu/shaper.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/tmu/shaper.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _SHAPER_H_
|
||||
#define _SHAPER_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/uart.h b/drivers/net/pfe_eth/pfe/uart.h
|
||||
index 483d446..2268430 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/uart.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/uart.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _UART_H_
|
||||
#define _UART_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/util/eape.h b/drivers/net/pfe_eth/pfe/util/eape.h
|
||||
index 07344dc..77af2d4 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/util/eape.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/util/eape.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _EAPE_H_
|
||||
#define _EAPE_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/util/efet.h b/drivers/net/pfe_eth/pfe/util/efet.h
|
||||
index 12d0310..eed87fe 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/util/efet.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/util/efet.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _UTIL_EFET_H_
|
||||
#define _UTIL_EFET_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe/util/inq.h b/drivers/net/pfe_eth/pfe/util/inq.h
|
||||
index 73d1acb..7ee008b 100644
|
||||
--- a/drivers/net/pfe_eth/pfe/util/inq.h
|
||||
+++ b/drivers/net/pfe_eth/pfe/util/inq.h
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _INQ_H_
|
||||
#define _INQ_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
|
||||
index 2f4c385..e252fcf 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_driver.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_driver.c
|
||||
@@ -1,27 +1,8 @@
|
||||
/*
|
||||
- * (C) Copyright 2011
|
||||
- * Author : Mindspeed Technologes
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- * */
|
||||
-
|
||||
-
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#include "hal.h"
|
||||
#include "pfe/pfe.h"
|
||||
#include "pfe_driver.h"
|
||||
diff --git a/drivers/net/pfe_eth/pfe_driver.h b/drivers/net/pfe_eth/pfe_driver.h
|
||||
index 4d2e8b6..2ef8e5c 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_driver.h
|
||||
+++ b/drivers/net/pfe_eth/pfe_driver.h
|
||||
@@ -1,26 +1,8 @@
|
||||
/*
|
||||
- * (C) Copyright 2011
|
||||
- * Author : Mindspeed Technologes
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- * */
|
||||
-
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef __PFE_DRIVER_H__
|
||||
#define __PFE_DRIVER_H__
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
|
||||
index 4a935ca..528ede9 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.c
|
||||
@@ -1,3 +1,8 @@
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
//#include <asm/arch/hardware.h>
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
|
||||
index af6191d..358fa58 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.h
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.h
|
||||
@@ -1,26 +1,8 @@
|
||||
/*
|
||||
- * (C) Copyright 2011
|
||||
- * Author : Mindspeed Technologes
|
||||
- *
|
||||
- * See file CREDITS for list of people who contributed to this
|
||||
- * project.
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or
|
||||
- * modify it under the terms of the GNU General Public License as
|
||||
- * published by the Free Software Foundation; either version 2 of
|
||||
- * the License, or (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
- * MA 02111-1307 USA
|
||||
- * */
|
||||
-
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
#ifndef _LS1012a_ETH_H_
|
||||
#define _LS1012a_ETH_H_
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
|
||||
index 5957afd..e190514 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_firmware.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_firmware.c
|
||||
@@ -1,4 +1,8 @@
|
||||
-
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
|
||||
/** @file
|
||||
* Contains all the functions to handle parsing and loading of PE firmware files.
|
||||
diff --git a/drivers/net/pfe_eth/pfe_firmware.h b/drivers/net/pfe_eth/pfe_firmware.h
|
||||
index 2823162..ecae3e3 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_firmware.h
|
||||
+++ b/drivers/net/pfe_eth/pfe_firmware.h
|
||||
@@ -1,4 +1,8 @@
|
||||
-
|
||||
+/*
|
||||
+* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||||
+*
|
||||
+* SPDX-License-Identifier:GPL-2.0+
|
||||
+*/
|
||||
|
||||
/** @file
|
||||
* Contains all the defines to handle parsing and loading of PE firmware files.
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,40 +0,0 @@ |
||||
From 9722009432a5553b11c8e0a04a275654de11dbc4 Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Mon, 13 Jun 2016 16:33:06 +0530
|
||||
Subject: [PATCH 53/93] armv8: arch-fsl-layerscape: Update name of Soc
|
||||
|
||||
Update the name of the Soc.
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 +++++++-------
|
||||
1 file changed, 7 insertions(+), 7 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
index e4ff990..7a943be 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
|
||||
@@ -8,13 +8,13 @@
|
||||
#define _FSL_LAYERSCAPE_CPU_H
|
||||
|
||||
static struct cpu_type cpu_type_list[] = {
|
||||
- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
|
||||
- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
|
||||
- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
|
||||
- CPU_TYPE_ENTRY(LS1043, LS1043, 4),
|
||||
- CPU_TYPE_ENTRY(LS1023, LS1023, 2),
|
||||
- CPU_TYPE_ENTRY(LS2040, LS2040, 4),
|
||||
- CPU_TYPE_ENTRY(LS1012, LS1012, 1),
|
||||
+ CPU_TYPE_ENTRY(LS2080A, LS2080, 8),
|
||||
+ CPU_TYPE_ENTRY(LS2085A, LS2085, 8),
|
||||
+ CPU_TYPE_ENTRY(LS2045A, LS2045, 4),
|
||||
+ CPU_TYPE_ENTRY(LS1043A, LS1043, 4),
|
||||
+ CPU_TYPE_ENTRY(LS1023A, LS1023, 2),
|
||||
+ CPU_TYPE_ENTRY(LS2040A, LS2040, 4),
|
||||
+ CPU_TYPE_ENTRY(LS1012A, LS1012, 1),
|
||||
};
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,33 +0,0 @@ |
||||
From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Mon, 13 Jun 2016 17:29:59 +0530
|
||||
Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings
|
||||
|
||||
DDR timigs displayed for LS1012A were half of true value.
|
||||
Updated DDR value to 1000 MT/s.
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
---
|
||||
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
index 63e5bed..a4dde5b 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
|
||||
@@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
|
||||
- if (ver == SVR_LS1012)
|
||||
+ if (ver == SVR_LS1012){
|
||||
sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
|
||||
-
|
||||
+ sys_info->freq_ddrbus *=2;
|
||||
+ }
|
||||
#define HWA_CGA_M1_CLK_SEL 0xe0000000
|
||||
#define HWA_CGA_M1_CLK_SHIFT 29
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,101 +0,0 @@ |
||||
From 0431dc26df78b00cef190f45f203a1598b4ba428 Mon Sep 17 00:00:00 2001
|
||||
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
|
||||
Date: Tue, 14 Jun 2016 10:07:41 +0530
|
||||
Subject: [PATCH 55/93] Add License file for PPFE firmware bins
|
||||
|
||||
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
drivers/net/pfe_eth/Freescale-Binary-EULA.txt | 80 +++++++++++++++++++++++++
|
||||
1 file changed, 80 insertions(+)
|
||||
create mode 100644 drivers/net/pfe_eth/Freescale-Binary-EULA.txt
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/Freescale-Binary-EULA.txt b/drivers/net/pfe_eth/Freescale-Binary-EULA.txt
|
||||
new file mode 100644
|
||||
index 0000000..628fa93
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/pfe_eth/Freescale-Binary-EULA.txt
|
||||
@@ -0,0 +1,80 @@
|
||||
+Copyright © 2016, Freescale Semiconductor, Inc. All rights reserved.
|
||||
+
|
||||
+Software License Agreement (.Agreement.)
|
||||
+
|
||||
+ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE ACCOMPANYING BINARY SOFTWARE
|
||||
+CONSTITUTES LICENSEE'S ACCEPTANCE OF THE TERMS AND CONDITIONS OF THIS
|
||||
+AGREEMENT.
|
||||
+
|
||||
+Licensed Software. .Binary Software. means software in binary form specified
|
||||
+in ANNEX A Subject to the terms and conditions of this Agreement, Freescale
|
||||
+Semiconductor, Inc., a 100% affiliated company of NXP Semiconductors N.V.
|
||||
+which will be renamed in due course ("NXP"), grants to Licensee a worldwide,
|
||||
+non-exclusive, and royalty-free license to use, reproduce, and distribute the
|
||||
+Binary Software in its complete and unmodified binary form as provided by NXP.
|
||||
+
|
||||
+Restrictions. Licensee must reproduce the NXP copyright notice above with each
|
||||
+binary copy of the Binary Software. Licensee must not reverse engineer,
|
||||
+decompile, disassemble or modify in any way the Binary Software. Licensee must
|
||||
+not use the Binary Software in violation of any applicable law or regulation.
|
||||
+This Agreement shall automatically terminate upon Licensee's breach of any
|
||||
+term or condition of this Agreement in which case, Licensee shall destroy all
|
||||
+copies of the Binary Software.
|
||||
+
|
||||
+Warranty Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NXP EXPRESSLY
|
||||
+DISCLAIMS ANY WARRANTY FOR THE BINARY SOFTWARE. THE BINARY SOFTWARE IS
|
||||
+PROVIDED .AS IS., WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
|
||||
+INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
+FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. LICENSEE ASSUMES
|
||||
+THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE BINARY SOFTWARE,
|
||||
+OR ANY SYSTEMS LICENSEE DESIGNS USING THE BINARY SOFTWARE (IF ANY). WITHOUT
|
||||
+LIMITING THE GENERALITY OF THE FOREGOING, NXP DOES NOT WARRANT THAT THE BINARY
|
||||
+SOFTWARE IS ERROR-FREE OR WILL OPERATE WITHOUT INTERRUPTION, AND NXP GRANTS
|
||||
+NO WARRANTY REGARDING ITS USE OR THE RESULTS THEREFROM, INCLUDING ITS
|
||||
+CORRECTNESS, ACCURACY, OR RELIABILITY.
|
||||
+
|
||||
+Limitation of Liability. IN NO EVENT WILL NXP, OR ANY OF NXP'S LICENSORS HAVE
|
||||
+ANY LIABILITY HEREUNDER FOR ANY INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES,
|
||||
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER FOR BREACH OF CONTRACT,
|
||||
+TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, ARISING OUT OF THIS AGREEMENT,
|
||||
+ INCLUDING DAMAGES FOR LOSS OF PROFITS, OR THE COST OF PROCUREMENT OF
|
||||
+ SUBSTITUTE GOODS, EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
+ SUCH DAMAGES. NXP.S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES
|
||||
+ WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR THE BINARY
|
||||
+ SOFTWARE SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID
|
||||
+ BY LICENSEE TO NXP IN CONNECTION WITH THE BINARY SOFTWARE TO WHICH LOSSES OR
|
||||
+ DAMAGES ARE CLAIMED.
|
||||
+
|
||||
+Trade Compliance. Licensee shall comply with all applicable export and import
|
||||
+ control laws and regulations including but not limited to the US Export
|
||||
+ Administration Regulation (including prohibited party lists issued by other
|
||||
+ federal governments), Catch-all regulations and all national and international
|
||||
+ embargoes. Licensee will not knowingly transfer, divert, export or re-export,
|
||||
+ directly or indirectly, any product, software, including software source code,
|
||||
+ or technology restricted by such regulations or by other applicable national
|
||||
+ regulations, received from the other party under this Agreement, or any direct
|
||||
+ product of such software or technical data to any person, firm, entity, country
|
||||
+ or destination to which such transfer, diversion, export or re-export is
|
||||
+ restricted or prohibited, without obtaining prior written authorization from
|
||||
+ the applicable competent government authorities to the extent required by
|
||||
+ those laws.
|
||||
+
|
||||
+Restrictions, Warranty Disclaimer, Limitation of Liability, Trade Compliance,
|
||||
+ and Governing Law shall survive termination or expiration of this Agreement.
|
||||
+
|
||||
+Governing Law. This Agreement will be governed by, construed, and enforced in
|
||||
+ accordance with the laws of the State of Texas, USA, without regard to
|
||||
+ conflicts of laws principles, will apply to all matters relating to this
|
||||
+ Agreement or the binary software, and Licensee agrees that any litigation will
|
||||
+ be subject to the exclusive jurisdiction of the state or federal courts Texas,
|
||||
+ USA. The United Nations Convention on Contracts for the International Sale of
|
||||
+ Goods will not apply to this Agreement.
|
||||
+
|
||||
+
|
||||
+ANNEX A
|
||||
+BINARY SOFTWARE
|
||||
+Only software in binary form may be provided under this Agreement
|
||||
+Here is a list of software covered by this Agreement:
|
||||
+class_sbl_elf.fw
|
||||
+tmu_sbl_elf.fw
|
||||
+util_sbl_elf.fw
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,93 +0,0 @@ |
||||
From 22424b4b25faefec704556d47751ad54c811ee09 Mon Sep 17 00:00:00 2001
|
||||
From: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Date: Wed, 15 Jun 2016 15:45:12 +0800
|
||||
Subject: [PATCH 56/93] mmc: fsl_esdhc: disable sdhc2 when no card inserted
|
||||
for ls1012aqds
|
||||
|
||||
This is a temporary workaround patch for ls1012aqds becasue there
|
||||
was host controller hardware issue found on some QDS boards when
|
||||
there was no eMMC adapter card inserted. This would cause below
|
||||
continious error messages in linux. So this patch is to disable
|
||||
sdhc2 when finding there isn't card inserted.
|
||||
"mmc1: Controller never released inhibit bit(s)."
|
||||
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 11 +++++++++++
|
||||
drivers/mmc/fsl_esdhc.c | 9 +++++++++
|
||||
include/fdt_support.h | 4 +++-
|
||||
3 files changed, 23 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index b7365e8..56004ea 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -161,6 +161,17 @@ int select_i2c_ch_pca9547(u8 ch)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+int mmc_check_sdhc2_card(void)
|
||||
+{
|
||||
+ u8 card_id;
|
||||
+
|
||||
+ card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
|
||||
+ if (card_id == 0x7)
|
||||
+ return 0;
|
||||
+ else
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
int dram_init(void)
|
||||
{
|
||||
mmdc_init();
|
||||
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
|
||||
index 2c6e175..98f3cca 100644
|
||||
--- a/drivers/mmc/fsl_esdhc.c
|
||||
+++ b/drivers/mmc/fsl_esdhc.c
|
||||
@@ -774,6 +774,11 @@ int fsl_esdhc_mmc_init(bd_t *bis)
|
||||
#endif
|
||||
}
|
||||
|
||||
+__weak int mmc_check_sdhc2_card(void)
|
||||
+{
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
||||
void mmc_adapter_card_type_ident(void)
|
||||
{
|
||||
@@ -817,6 +822,7 @@ void mmc_adapter_card_type_ident(void)
|
||||
void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
||||
{
|
||||
const char *compat = "fsl,esdhc";
|
||||
+ const char *compat1 = "fsl,ls1012a-esdhc1";
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
||||
if (!hwconfig("esdhc")) {
|
||||
@@ -839,5 +845,8 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
||||
#endif
|
||||
do_fixup_by_compat(blob, compat, "status", "okay",
|
||||
4 + 1, 1);
|
||||
+ if (!mmc_check_sdhc2_card())
|
||||
+ do_fixup_by_compat(blob, compat1, "status", "disabled",
|
||||
+ 4 + 1, 1);
|
||||
}
|
||||
#endif
|
||||
diff --git a/include/fdt_support.h b/include/fdt_support.h
|
||||
index 296add0..2e66eb1 100644
|
||||
--- a/include/fdt_support.h
|
||||
+++ b/include/fdt_support.h
|
||||
@@ -240,7 +240,9 @@ int arch_fixup_memory_node(void *blob);
|
||||
|
||||
int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
|
||||
u32 height, u32 stride, const char *format);
|
||||
-
|
||||
+#ifdef CONFIG_FSL_ESDHC
|
||||
+int mmc_check_sdhc2_card(void);
|
||||
+#endif
|
||||
#endif /* ifdef CONFIG_OF_LIBFDT */
|
||||
|
||||
#ifdef USE_HOSTCC
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,92 +0,0 @@ |
||||
From 0ff26c3761e5a17d21e7ee0bd9a2068f55c84d55 Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Wed, 15 Jun 2016 14:57:08 +0800
|
||||
Subject: [PATCH 57/93] driver: spi: Fix DSPI bug after adding exceed 16MB for
|
||||
QSPI
|
||||
|
||||
=> sf probe 1:0
|
||||
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total
|
||||
16 MiB
|
||||
=> mw.l 80000000 55555555 1100
|
||||
=> mw.l 80020000 aaaaaaaa 1100
|
||||
=> sf erase 0 +1100
|
||||
SF: 65536 bytes @ 0x0 Erased: OK
|
||||
=> sf write 80020000 0 1100
|
||||
device 0 offset 0x0, size 0x1100
|
||||
SF: 4352 bytes @ 0x0 Written: OK
|
||||
=> sf read 80000000 0 1100
|
||||
device 0 offset 0x0, size 0x1100
|
||||
SF: 4352 bytes @ 0x0 Read: OK
|
||||
=> cmp.b 80000000 80020000 1100
|
||||
byte at 0x00000000800010fe (0xff) != byte at 0x00000000800210fe (0xaa)
|
||||
Total of 4350 byte(s) were the same
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 21 +++++++++++++++------
|
||||
1 file changed, 15 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index b0f09ab..e04bd55 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -326,8 +326,11 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
+ if (flash->size > SPI_FLASH_16MB_BOUN)
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ else
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN;
|
||||
|
||||
- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
@@ -353,7 +356,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
|
||||
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
|
||||
cmd[2], cmd[3], erase_addr);
|
||||
|
||||
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
|
||||
+ ret = spi_flash_write_common(flash, cmd, cmdsz, NULL, 0);
|
||||
if (ret < 0) {
|
||||
debug("SF: erase failed\n");
|
||||
break;
|
||||
@@ -385,8 +388,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
-
|
||||
- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ if (flash->size > SPI_FLASH_16MB_BOUN)
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ else
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN;
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
@@ -418,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
|
||||
debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
|
||||
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
|
||||
|
||||
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
|
||||
+ ret = spi_flash_write_common(flash, cmd, cmdsz,
|
||||
buf + actual, chunk_len);
|
||||
if (ret < 0) {
|
||||
debug("SF: write failed\n");
|
||||
@@ -482,7 +487,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
|
||||
return 0;
|
||||
}
|
||||
|
||||
- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ if (flash->size > SPI_FLASH_16MB_BOUN)
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
|
||||
+ else
|
||||
+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
|
||||
+
|
||||
cmd = calloc(1, cmdsz);
|
||||
if (!cmd) {
|
||||
debug("SF: Failed to allocate cmd\n");
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,56 +0,0 @@ |
||||
From 0499ca266f668c9d72217631151f3b6e15350134 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Wed, 15 Jun 2016 17:42:51 +0530
|
||||
Subject: [PATCH 58/93] mmc: fsl_esdhc: disable sdhc2 when no card inserted
|
||||
for ls1012ardb
|
||||
|
||||
This is a temporary workaround patch for ls1012ardb becasue there
|
||||
was host controller hardware issue found on some RDB boards when
|
||||
there was no eMMC adapter card inserted. This would cause below
|
||||
continious error messages in linux. So this patch is to disable
|
||||
sdhc2 when finding there isn't card inserted.
|
||||
"mmc1: Controller never released inhibit bit(s)."
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 24 ++++++++++++++++++++++++
|
||||
1 file changed, 24 insertions(+)
|
||||
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index 90cbd5e..ad4d8ee 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -171,6 +171,30 @@ int board_early_init_f(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+int mmc_check_sdhc2_card(void)
|
||||
+{
|
||||
+ u8 io = 0;
|
||||
+ u8 is_card = 0;
|
||||
+
|
||||
+ /* Initialize i2c early for Serial flash bank information */
|
||||
+ i2c_set_bus_num(0);
|
||||
+
|
||||
+ if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
|
||||
+ printf("Error reading i2c boot information!\n");
|
||||
+ return 0; /* Don't want to hang() on this error */
|
||||
+ }
|
||||
+
|
||||
+ io = io & 0x0c;
|
||||
+
|
||||
+ switch (io) {
|
||||
+ case 0:
|
||||
+ case 8:
|
||||
+ is_card = 1;
|
||||
+ }
|
||||
+
|
||||
+ return is_card;
|
||||
+}
|
||||
+
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,110 +0,0 @@ |
||||
From 4df84c450d7ce450986e5f1dc5e7ab164b9e0e32 Mon Sep 17 00:00:00 2001
|
||||
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Date: Fri, 17 Jun 2016 10:04:34 +0530
|
||||
Subject: [PATCH 59/93] armv8: ls1012a: Make FAT and EXT2 commands support
|
||||
common
|
||||
|
||||
Makes FAT and EXT2 commands support common for LS1012A QDS,
|
||||
RDB and FRDM.
|
||||
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
---
|
||||
include/configs/ls1012a_common.h | 5 +++++
|
||||
include/configs/ls1012afrdm.h | 1 -
|
||||
include/configs/ls1012aqds.h | 6 ------
|
||||
include/configs/ls1012ardb.h | 6 ------
|
||||
4 files changed, 5 insertions(+), 13 deletions(-)
|
||||
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 2895e7a..7c0e64f 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -184,6 +184,11 @@
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
|
||||
+/* Used by SCSI, MMC and USB */
|
||||
+#define CONFIG_CMD_FAT
|
||||
+#define CONFIG_DOS_PARTITION
|
||||
+#define CONFIG_CMD_EXT2
|
||||
+
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LS1012A_COMMON_H */
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 5e619c1..432317d 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -38,7 +38,6 @@
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
-#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CONFIG_USB_DWC3
|
||||
#define CONFIG_USB_DWC3_GADGET
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index cc8e0fc..c06cfbd 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -34,8 +34,6 @@
|
||||
#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#define CONFIG_GENERIC_MMC
|
||||
-#define CONFIG_CMD_FAT
|
||||
-#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
#endif /* CONFIG_EMU */
|
||||
|
||||
@@ -45,9 +43,6 @@
|
||||
#define CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_CMD_SCSI
|
||||
-#define CONFIG_CMD_FAT
|
||||
-#define CONFIG_CMD_EXT2
|
||||
-#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
|
||||
@@ -204,7 +199,6 @@
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
-#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CONFIG_USB_DWC3
|
||||
#define CONFIG_USB_DWC3_GADGET
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index e94df74..f6b3f28 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -39,7 +39,6 @@
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
-#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CONFIG_USB_DWC3
|
||||
#define CONFIG_USB_DWC3_GADGET
|
||||
@@ -67,8 +66,6 @@
|
||||
#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#define CONFIG_GENERIC_MMC
|
||||
-#define CONFIG_CMD_FAT
|
||||
-#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
#endif /* CONFIG_EMU */
|
||||
|
||||
@@ -78,9 +75,6 @@
|
||||
#define CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_CMD_SCSI
|
||||
-#define CONFIG_CMD_FAT
|
||||
-#define CONFIG_CMD_EXT2
|
||||
-#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,58 +0,0 @@ |
||||
From 4733ade3cdc2b2fcc960d72b6ad9009a3ada38cf Mon Sep 17 00:00:00 2001
|
||||
From: Tang Yuantian <Yuantian.Tang@nxp.com>
|
||||
Date: Fri, 24 Jun 2016 10:59:46 +0800
|
||||
Subject: [PATCH 60/93] ls1012: sata: add sata support
|
||||
|
||||
So add sata configuation for ls1012 soc.
|
||||
|
||||
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++
|
||||
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +++++++
|
||||
2 files changed, 16 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
index 0a170eb..ab902ce 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
|
||||
@@ -328,10 +328,19 @@ int sata_init(void)
|
||||
{
|
||||
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
|
||||
|
||||
+#if defined(CONFIG_LS1043A)
|
||||
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
|
||||
out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
|
||||
out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
|
||||
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
|
||||
+#elif defined(CONFIG_LS1012A)
|
||||
+ out_le32(&ccsr_ahci->ppcfg, LS1012A_PORT_PHY1);
|
||||
+ out_le32(&ccsr_ahci->pp2c, LS1012A_PORT_PHY2);
|
||||
+ out_le32(&ccsr_ahci->pp3c, LS1012A_PORT_PHY3);
|
||||
+ out_le32(&ccsr_ahci->pp4c, LS1012A_PORT_PHY4);
|
||||
+ out_le32(&ccsr_ahci->pp5c, LS1012A_PORT_PHY5);
|
||||
+ out_le32(&ccsr_ahci->ptc, LS1012A_PORT_TRANS);
|
||||
+#endif
|
||||
|
||||
ahci_init((void __iomem *)CONFIG_SYS_SATA);
|
||||
scsi_scan(0);
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
|
||||
index 0822b49..8071114 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
|
||||
@@ -60,6 +60,13 @@ struct cpu_type {
|
||||
#define AHCI_PORT_PHY_3_CFG 0x0e081509
|
||||
#define AHCI_PORT_TRANS_CFG 0x08000029
|
||||
|
||||
+#define LS1012A_PORT_PHY1 0xa003fffe
|
||||
+#define LS1012A_PORT_PHY2 0x28184d1b
|
||||
+#define LS1012A_PORT_PHY3 0x0e081906
|
||||
+#define LS1012A_PORT_PHY4 0x064a0813
|
||||
+#define LS1012A_PORT_PHY5 0x3ffc96a4
|
||||
+#define LS1012A_PORT_TRANS 0x08000029
|
||||
+
|
||||
/* AHCI (sata) register map */
|
||||
struct ccsr_ahci {
|
||||
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,75 +0,0 @@ |
||||
From e84c8c3f444aae4359cd4d60fabd3d2145d011b5 Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Fri, 24 Jun 2016 11:03:38 +0530
|
||||
Subject: [PATCH 61/93] ARMv8: freescale: Consolidate PPA flags under a single
|
||||
flag
|
||||
|
||||
[context adjustment]
|
||||
|
||||
LS1012A places PPA binary on QSPI flash instead of NOR.
|
||||
So, depricating CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
|
||||
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
|
||||
by addition of a new QSPI specific flag.
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
|
||||
---
|
||||
arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 4 ++--
|
||||
arch/arm/include/asm/fsl_secure_boot.h | 2 +-
|
||||
include/configs/ls1043ardb.h | 4 ++--
|
||||
3 files changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
|
||||
index 116e164..8986260 100644
|
||||
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
|
||||
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
|
||||
@@ -163,7 +163,7 @@ static int ppa_parse_firmware_fit_image(const void **raw_image_addr,
|
||||
void *ppa_addr;
|
||||
int ret;
|
||||
|
||||
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
|
||||
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
ppa_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
|
||||
#else
|
||||
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
|
||||
@@ -197,7 +197,7 @@ int sec_firmware_validate(void)
|
||||
{
|
||||
void *ppa_addr;
|
||||
|
||||
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
|
||||
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
ppa_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
|
||||
#else
|
||||
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
|
||||
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
|
||||
index c973255..b2e9105 100644
|
||||
--- a/arch/arm/include/asm/fsl_secure_boot.h
|
||||
+++ b/arch/arm/include/asm/fsl_secure_boot.h
|
||||
@@ -104,7 +104,7 @@
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LS_PPA
|
||||
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
|
||||
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
#ifdef CONFIG_LS1043A
|
||||
#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
|
||||
#endif
|
||||
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
|
||||
index af8b441..46818e8 100644
|
||||
--- a/include/configs/ls1043ardb.h
|
||||
+++ b/include/configs/ls1043ardb.h
|
||||
@@ -14,8 +14,8 @@
|
||||
#define CONFIG_ARMV8_PSCI
|
||||
#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
|
||||
-#define CONFIG_SYS_LS_PPA_FW_IN_NOR
|
||||
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
|
||||
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000
|
||||
#endif
|
||||
#endif
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,27 +0,0 @@ |
||||
From f1b3374b2f99b30795423a4ae514e634bb84a1d9 Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Fri, 24 Jun 2016 10:32:59 +0530
|
||||
Subject: [PATCH 62/93] ARMv8: freescale: Fix the address map of SCFG
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
index a7bc2a4..696d0a3 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
|
||||
@@ -450,7 +450,7 @@ struct ccsr_scfg {
|
||||
u32 pfebsbcr;
|
||||
u8 res_460[0x484-0x460];
|
||||
u32 mdioselcr;
|
||||
- u8 res_468[0x600-0x468];
|
||||
+ u8 res_488[0x600-0x488];
|
||||
u32 scratchrw[4];
|
||||
u8 res_610[0x680-0x610];
|
||||
u32 corebcr;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,157 +0,0 @@ |
||||
From 1882af9f2c7533c6cd2dea5811b4e69f9a151f29 Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Fri, 24 Jun 2016 10:45:39 +0530
|
||||
Subject: [PATCH 63/93] board: freescale: ls1012a: Enable secure DDR on
|
||||
LS1012A platforms
|
||||
|
||||
PPA binary needs to be relocated on secure DDR, hence marking out
|
||||
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
|
||||
is set
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++
|
||||
board/freescale/ls1012afrdm/ls1012afrdm.c | 28 +++++++++++++++++++++
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 28 +++++++++++++++++++++
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 28 +++++++++++++++++++++
|
||||
include/configs/ls1012a_common.h | 1 +
|
||||
5 files changed, 88 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
index 679be6c..efaa79a 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
@@ -222,6 +222,9 @@
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
|
||||
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
+
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
index 6856250..c691a76 100644
|
||||
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
@@ -176,3 +176,31 @@ int ft_board_setup(void *blob, bd_t *bd)
|
||||
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+void dram_init_banksize(void)
|
||||
+{
|
||||
+ /*
|
||||
+ * gd->secure_ram tracks the location of secure memory.
|
||||
+ * It was set as if the memory starts from 0.
|
||||
+ * The address needs to add the offset of its bank.
|
||||
+ */
|
||||
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
|
||||
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
|
||||
+ gd->bd->bi_dram[1].size = gd->ram_size -
|
||||
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
||||
+ gd->secure_ram = gd->bd->bi_dram[1].start +
|
||||
+ gd->secure_ram -
|
||||
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
||||
+#endif
|
||||
+ } else {
|
||||
+ gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
||||
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
|
||||
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
||||
+#endif
|
||||
+ }
|
||||
+}
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index 56004ea..516f0c3 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -240,3 +240,31 @@ int ft_board_setup(void *blob, bd_t *bd)
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
+
|
||||
+void dram_init_banksize(void)
|
||||
+{
|
||||
+ /*
|
||||
+ * gd->secure_ram tracks the location of secure memory.
|
||||
+ * It was set as if the memory starts from 0.
|
||||
+ * The address needs to add the offset of its bank.
|
||||
+ */
|
||||
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
|
||||
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
|
||||
+ gd->bd->bi_dram[1].size = gd->ram_size -
|
||||
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
||||
+ gd->secure_ram = gd->bd->bi_dram[1].start +
|
||||
+ gd->secure_ram -
|
||||
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
||||
+#endif
|
||||
+ } else {
|
||||
+ gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
||||
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
|
||||
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
||||
+#endif
|
||||
+ }
|
||||
+}
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index ad4d8ee..8340f14 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -235,3 +235,31 @@ int ft_board_setup(void *blob, bd_t *bd)
|
||||
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+void dram_init_banksize(void)
|
||||
+{
|
||||
+ /*
|
||||
+ * gd->secure_ram tracks the location of secure memory.
|
||||
+ * It was set as if the memory starts from 0.
|
||||
+ * The address needs to add the offset of its bank.
|
||||
+ */
|
||||
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
|
||||
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
|
||||
+ gd->bd->bi_dram[1].size = gd->ram_size -
|
||||
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
||||
+ gd->secure_ram = gd->bd->bi_dram[1].start +
|
||||
+ gd->secure_ram -
|
||||
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
|
||||
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
||||
+#endif
|
||||
+ } else {
|
||||
+ gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
||||
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
|
||||
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
||||
+#endif
|
||||
+ }
|
||||
+}
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 7c0e64f..4c7c697 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -36,6 +36,7 @@
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
||||
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 25000000 /* 12MHz */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,64 +0,0 @@ |
||||
From 31f17073ffb1501574ad4cb8dffd507dee40e69a Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Thu, 16 Jun 2016 13:49:17 +0530
|
||||
Subject: [PATCH 64/93] board: freescale: ls1012a: Intergrate and enable PPA
|
||||
on LS1012ARDB
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 10 ++++++++++
|
||||
include/configs/ls1012ardb.h | 9 +++++++++
|
||||
2 files changed, 19 insertions(+)
|
||||
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index 8340f14..7f7503c 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -198,6 +198,9 @@ int mmc_check_sdhc2_card(void)
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
+#ifdef CONFIG_FSL_LS_PPA
|
||||
+ u64 ppa_entry;
|
||||
+#endif
|
||||
/*
|
||||
* Set CCI-400 control override register to enable barrier
|
||||
* transaction
|
||||
@@ -216,6 +219,13 @@ int board_init(void)
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_FSL_LS_PPA
|
||||
+ ppa_init_pre(&ppa_entry);
|
||||
+
|
||||
+ if (ppa_entry)
|
||||
+ ppa_init_entry((void *)ppa_entry);
|
||||
+#endif
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index f6b3f28..fdaea3e 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -9,6 +9,15 @@
|
||||
|
||||
#include "ls1012a_common.h"
|
||||
|
||||
+#define CONFIG_FSL_LS_PPA
|
||||
+#if defined(CONFIG_FSL_LS_PPA)
|
||||
+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
+
|
||||
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
+#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
|
||||
+#endif
|
||||
+#endif
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,47 +0,0 @@ |
||||
From 39f95bb22c03b18ac6c4ef1b4485414dd4a303cb Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Fri, 24 Jun 2016 14:37:42 +0530
|
||||
Subject: [PATCH 65/93] docs: fsl-ppa: Add documentation for PPA trusted FW
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
doc/README.fsl-ppa | 26 ++++++++++++++++++++++++++
|
||||
1 file changed, 26 insertions(+)
|
||||
create mode 100644 doc/README.fsl-ppa
|
||||
|
||||
diff --git a/doc/README.fsl-ppa b/doc/README.fsl-ppa
|
||||
new file mode 100644
|
||||
index 0000000..76cd01f
|
||||
--- /dev/null
|
||||
+++ b/doc/README.fsl-ppa
|
||||
@@ -0,0 +1,26 @@
|
||||
+PPA FW for U-boot
|
||||
+
|
||||
+Summary
|
||||
+=======
|
||||
+PPA is a trusted firmware for ARMv8 , that handles smc calls from lower
|
||||
+exception levels, like power state co-ordination interface call or
|
||||
+smc calls to trusted OS from the Linux kernel.
|
||||
+
|
||||
+Notes
|
||||
+=====
|
||||
+
|
||||
+1. Currenly, u-boot run at the highest exception level processor
|
||||
+ supported, which is EL3 in case of ARMv8, if PPA FW is incorporated
|
||||
+ U-boot copies it to secure location in DDR.
|
||||
+2. During init U-boot passes control to PPA FW and before returning
|
||||
+ the core jumps to EL2.
|
||||
+
|
||||
+Using PPA
|
||||
+=========
|
||||
+1. Ensure CONFIG_FSL_LS_PPA is set for your platform
|
||||
+2. Program PPA binary on address CONFIG_SYS_LS_PPA_FW_ADDR on flash
|
||||
+
|
||||
+Contributors
|
||||
+============
|
||||
+ Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
+ Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,113 +0,0 @@ |
||||
From 35efc0f34b56ca9d5fb5d080d5de0833ded7e3b8 Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Tue, 21 Jun 2016 13:25:12 +0530
|
||||
Subject: [PATCH 66/93] armv8:pfe Enable UDP checksum for proper tftp
|
||||
operation
|
||||
|
||||
1. Add CONFIG_UDP_CHECKSUM flag to perform UDP checksum in S/W
|
||||
instead of hardware
|
||||
2. Rx descriptor model changed back to original
|
||||
removed strobe mode
|
||||
3. Send more than one dummy packets to bring HIF BD to idle state
|
||||
|
||||
Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
|
||||
---
|
||||
common/cmd_pfe_commands.c | 12 +++++++-----
|
||||
drivers/net/pfe_eth/pfe_driver.c | 19 +++----------------
|
||||
include/configs/ls1012a_common.h | 1 +
|
||||
3 files changed, 11 insertions(+), 21 deletions(-)
|
||||
|
||||
diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
|
||||
index 92917e0..3575ad4 100644
|
||||
--- a/common/cmd_pfe_commands.c
|
||||
+++ b/common/cmd_pfe_commands.c
|
||||
@@ -929,7 +929,7 @@ static void send_dummy_pkt_to_hif(void)
|
||||
|
||||
static void pfe_command_stop(int argc, char * const argv[])
|
||||
{
|
||||
- int id;
|
||||
+ int id, hif_stop_loop = 10;
|
||||
u32 rx_status;
|
||||
printf("Stopping PFE... \n");
|
||||
|
||||
@@ -937,10 +937,12 @@ static void pfe_command_stop(int argc, char * const argv[])
|
||||
hif_rx_desc_disable();
|
||||
|
||||
/*If HIF Rx BDP is busy send a dummy packet */
|
||||
- rx_status = readl(HIF_RX_STATUS);
|
||||
- if(rx_status & BDP_CSR_RX_DMA_ACTV)
|
||||
- send_dummy_pkt_to_hif();
|
||||
- udelay(10);
|
||||
+ do {
|
||||
+ rx_status = readl(HIF_RX_STATUS);
|
||||
+ if (rx_status & BDP_CSR_RX_DMA_ACTV)
|
||||
+ send_dummy_pkt_to_hif();
|
||||
+ udelay(10);
|
||||
+ } while (hif_stop_loop--);
|
||||
|
||||
if(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
|
||||
printf("Unable to stop HIF\n");
|
||||
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
|
||||
index e252fcf..6774fb4 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_driver.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_driver.c
|
||||
@@ -37,13 +37,8 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
|
||||
bd = rx_desc->rxBase + rx_desc->rxToRead;
|
||||
|
||||
- if (bd->ctrl & BD_CTRL_DESC_EN) {
|
||||
- if(!(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)){
|
||||
- /*If BDP is not active give write strobe */
|
||||
- writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
|
||||
- }
|
||||
+ if (bd->ctrl & BD_CTRL_DESC_EN)
|
||||
return len; //No pending Rx packet
|
||||
- }
|
||||
|
||||
/* this len include hif_header(8bytes) */
|
||||
len = bd->ctrl & 0xFFFF;
|
||||
@@ -72,15 +67,10 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
*phy_port = hif_header->port_no;
|
||||
len -= sizeof(struct hif_header_s);
|
||||
|
||||
-#if defined(PFE_LS1012A_RESET_WA)
|
||||
- /* reset bd control field */
|
||||
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
|
||||
-#else
|
||||
/* reset bd control field */
|
||||
ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
|
||||
- /* If we use BD_CTRL_LAST_BD, rxToRead never changes */
|
||||
rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
|
||||
-#endif
|
||||
+
|
||||
bd->ctrl = ctrl;
|
||||
bd->status = 0;
|
||||
|
||||
@@ -363,11 +353,8 @@ static int hif_rx_desc_init(struct pfe *pfe)
|
||||
|
||||
memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
|
||||
|
||||
-#if defined(PFE_LS1012A_RESET_WA)
|
||||
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
|
||||
-#else
|
||||
ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
|
||||
-#endif
|
||||
+
|
||||
for (i=0; i < rx_desc->rxRingSize; i++) {
|
||||
bd_va->next = (unsigned long)(bd_pa + 1);
|
||||
bd_va->ctrl = ctrl;
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 4c7c697..47b8ec3 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -116,6 +116,7 @@
|
||||
#ifdef CONFIG_FSL_PPFE
|
||||
#define CONFIG_CMD_PFE_COMMANDS
|
||||
#define CONFIG_UTIL_PE_DISABLED
|
||||
+#define CONFIG_UDP_CHECKSUM
|
||||
|
||||
#endif
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,90 +0,0 @@ |
||||
From 8b6c309e5e55670f429730449d9921987636c8ec Mon Sep 17 00:00:00 2001
|
||||
From: Calvin Johnson <calvin.johnson@freescale.com>
|
||||
Date: Wed, 8 Jun 2016 17:04:58 +0530
|
||||
Subject: [PATCH 67/93] armv8: ls1012a: DDR optmizations
|
||||
|
||||
Enable DDR row-bank-column decoding. DDR address will
|
||||
be decoded as row-bank-column instead of bank-row-column.
|
||||
This will improve performance of serial data transfers.
|
||||
|
||||
Refresh cycle value must be selected based on the frequency
|
||||
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
|
||||
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
|
||||
value should be 0x0f3c8000.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012afrdm/ls1012afrdm.c | 4 ++--
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 4 ++--
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 4 ++--
|
||||
3 files changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
index c691a76..4b7902a 100644
|
||||
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
@@ -59,7 +59,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
|
||||
/* other parms */
|
||||
- out_be32(&mmdc->mdmisc, 0x00000680);
|
||||
+ out_be32(&mmdc->mdmisc, 0x00001680);
|
||||
out_be32(&mmdc->mpmur0, 0x00000800);
|
||||
out_be32(&mmdc->mdrwd, 0x00002000);
|
||||
out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
@@ -118,7 +118,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mapsr, 0x00001067);
|
||||
|
||||
/* refresh scheme */
|
||||
- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
|
||||
+ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
|
||||
|
||||
/* disable CON_REQ */
|
||||
out_be32(&mmdc->mdscr, 0x0);
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index 516f0c3..4ae8def 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -82,7 +82,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
|
||||
/* other parms */
|
||||
- out_be32(&mmdc->mdmisc, 0x00000680);
|
||||
+ out_be32(&mmdc->mdmisc, 0x00001680);
|
||||
out_be32(&mmdc->mpmur0, 0x00000800);
|
||||
out_be32(&mmdc->mdrwd, 0x00002000);
|
||||
out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
@@ -142,7 +142,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mapsr, 0x00001067);
|
||||
|
||||
/* refresh scheme */
|
||||
- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
|
||||
+ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
|
||||
|
||||
/* disable CON_REQ */
|
||||
out_be32(&mmdc->mdscr, 0x0);
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index 7f7503c..06e1f6b 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -88,7 +88,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
|
||||
/* other parms */
|
||||
- out_be32(&mmdc->mdmisc, 0x00000680);
|
||||
+ out_be32(&mmdc->mdmisc, 0x00001680);
|
||||
out_be32(&mmdc->mpmur0, 0x00000800);
|
||||
out_be32(&mmdc->mdrwd, 0x00002000);
|
||||
out_be32(&mmdc->mpodtctrl, 0x0000022a);
|
||||
@@ -148,7 +148,7 @@ void mmdc_init(void)
|
||||
out_be32(&mmdc->mapsr, 0x00001067);
|
||||
|
||||
/* refresh scheme */
|
||||
- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
|
||||
+ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
|
||||
|
||||
/* disable CON_REQ */
|
||||
out_be32(&mmdc->mdscr, 0x0);
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,29 +0,0 @@ |
||||
From 7715b8d4b833dfe3d997f21c8055d33975ed84c8 Mon Sep 17 00:00:00 2001
|
||||
From: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Date: Wed, 29 Jun 2016 16:03:33 +0530
|
||||
Subject: [PATCH 68/93] driver: pfe_eth: use #ifdef instead of #if
|
||||
|
||||
There is no need of checking the value of DEBUG,
|
||||
so use #ifdef preprocessor directive instead of #if.
|
||||
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
---
|
||||
drivers/net/pfe_eth/pfe_driver.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
|
||||
index 6774fb4..a3a3e49 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_driver.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_driver.c
|
||||
@@ -50,7 +50,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
|
||||
dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
|
||||
hif_header, len, hif_header->port_no, bd->status);
|
||||
|
||||
-#if DEBUG
|
||||
+#ifdef DEBUG
|
||||
{
|
||||
int i;
|
||||
unsigned char *p = (unsigned char *)hif_header;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,43 +0,0 @@ |
||||
From 4f217aaf4bca500f13b4c560a6bbb3708c8e5dc2 Mon Sep 17 00:00:00 2001
|
||||
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
|
||||
Date: Fri, 1 Jul 2016 04:37:53 +0530
|
||||
Subject: [PATCH 69/93] armv8:pfe:frdm Reset external PHYs before driver
|
||||
starts
|
||||
|
||||
- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started
|
||||
- Call reset_phy() before driver initialization
|
||||
|
||||
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
|
||||
Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
|
||||
---
|
||||
board/freescale/ls1012afrdm/eth.c | 1 +
|
||||
include/configs/ls1012afrdm.h | 1 -
|
||||
2 files changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
|
||||
index 90ed66b..be17310 100644
|
||||
--- a/board/freescale/ls1012afrdm/eth.c
|
||||
+++ b/board/freescale/ls1012afrdm/eth.c
|
||||
@@ -46,6 +46,7 @@ int board_eth_init(bd_t *bis)
|
||||
struct mdio_info mac1_mdio_info;
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
|
||||
+ reset_phy();
|
||||
|
||||
/*TODO Following config should be done for all boards, where is the right place to put this */
|
||||
out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 432317d..3de0cea 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -23,7 +23,6 @@
|
||||
#define EMAC2_PHY_ADDR 0x1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_REALTEK
|
||||
-#define CONFIG_RESET_PHY_R
|
||||
#endif
|
||||
/*
|
||||
* USB
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,45 +0,0 @@ |
||||
From 3df085e06da99123410e2394c8c6764ab0e98f3a Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Mon, 11 Jul 2016 16:18:28 +0530
|
||||
Subject: [PATCH 70/93] board: ls1012afrdm: overwrite
|
||||
CONFIG_EXTRA_ENV_SETTINGS
|
||||
|
||||
Kernel load address for ls1012afrdm is 0x96000000 because it has
|
||||
512MB of DDR.
|
||||
|
||||
So overwrite CONFIG_EXTRA_ENV_SETTINGS with updated kernel_load
|
||||
address.
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
include/configs/ls1012afrdm.h | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 3de0cea..622c774 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -59,4 +59,20 @@
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
+#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ "initrd_high=0xffffffff\0" \
|
||||
+ "verify=no\0" \
|
||||
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
+ "loadaddr=0x80100000\0" \
|
||||
+ "kernel_addr=0x100000\0" \
|
||||
+ "ramdisk_addr=0x800000\0" \
|
||||
+ "ramdisk_size=0x2000000\0" \
|
||||
+ "fdt_high=0xffffffffffffffff\0" \
|
||||
+ "initrd_high=0xffffffffffffffff\0" \
|
||||
+ "kernel_start=0xa00000\0" \
|
||||
+ "kernel_load=0x96000000\0" \
|
||||
+ "kernel_size=0x2800000\0" \
|
||||
+ "console=ttyAMA0,38400n8\0"
|
||||
+
|
||||
#endif /* __LS1012ARDB_H__ */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,58 +0,0 @@ |
||||
From e2a5bba97cd6e42b2b631bd17012aa26ffdb5f67 Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Tue, 12 Jul 2016 10:30:08 +0800
|
||||
Subject: [PATCH 71/93] driver: fsl_qspi: disable AHB buffer prefetch
|
||||
|
||||
Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
|
||||
When we enable the CONFIG_SYS_FSL_QSPI_AHB, we need this errata workaround.
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/spi/fsl_qspi.c | 12 +++++++++++-
|
||||
include/configs/ls1012a_common.h | 1 +
|
||||
2 files changed, 12 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
|
||||
index 09759fa..f1c87f5 100644
|
||||
--- a/drivers/spi/fsl_qspi.c
|
||||
+++ b/drivers/spi/fsl_qspi.c
|
||||
@@ -441,13 +441,23 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
|
||||
static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
|
||||
{
|
||||
struct fsl_qspi_regs *regs = priv->regs;
|
||||
+ int rx_size = 0x80;
|
||||
|
||||
/* AHB configuration for access buffer 0/1/2 .*/
|
||||
qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
|
||||
qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
|
||||
qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
|
||||
+
|
||||
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009282
|
||||
+ /*A-009282: QuadSPI data pre-fetch can result in incorrect data
|
||||
+ *Workaround: Keep the read data size to 64 bits (8 Bytes), which
|
||||
+ *disables the prefetch on the AHB buffer,and prevents this issue
|
||||
+ *from occurring.
|
||||
+ */
|
||||
+ rx_size = 0x1;
|
||||
+#endif
|
||||
qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
|
||||
- (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
|
||||
+ (rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
|
||||
|
||||
/* We only use the buffer3 */
|
||||
qspi_write32(priv->flags, ®s->buf0ind, 0);
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 47b8ec3..f0ae355 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -68,6 +68,7 @@
|
||||
#define FSL_QSPI_FLASH_SIZE (1 << 26)
|
||||
#define FSL_QSPI_FLASH_NUM 2
|
||||
#define CONFIG_SYS_FSL_QSPI_AHB
|
||||
+#define CONFIG_SYS_FSL_ERRATUM_A009282
|
||||
|
||||
/*
|
||||
* Environment
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,44 +0,0 @@ |
||||
From 31d5393ea4defd3872dc07264912f60ad627782b Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Tue, 12 Jul 2016 11:29:52 +0800
|
||||
Subject: [PATCH 72/93] driver: spi: fsl-qspi: remove compile Warnings
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Warnins log:
|
||||
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
|
||||
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
|
||||
memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/spi/fsl_qspi.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
|
||||
index f1c87f5..f521fe2 100644
|
||||
--- a/drivers/spi/fsl_qspi.c
|
||||
+++ b/drivers/spi/fsl_qspi.c
|
||||
@@ -389,6 +389,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
|
||||
{
|
||||
struct fsl_qspi_regs *regs = priv->regs;
|
||||
u32 mcr_reg;
|
||||
+ void *rx_addr = NULL;
|
||||
|
||||
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
|
||||
|
||||
@@ -396,8 +397,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
|
||||
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
|
||||
QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
|
||||
|
||||
+ rx_addr += priv->cur_amba_base + priv->sf_addr;
|
||||
/* Read out the data directly from the AHB buffer. */
|
||||
- memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
|
||||
+ memcpy(rxbuf, rx_addr, len);
|
||||
|
||||
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
|
||||
}
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,28 +0,0 @@ |
||||
From 3c41e8827ddcff313a518de19d630a42bbdca3b1 Mon Sep 17 00:00:00 2001
|
||||
From: Anji J <anji.jagarlmudi@freescale.com>
|
||||
Date: Fri, 8 Jul 2016 20:05:37 +0530
|
||||
Subject: [PATCH 73/93] armv8:pfe Change MDIO HOLDTIME value to 5
|
||||
|
||||
Per design/validation team suggestion use HOLDTIME value as 5.
|
||||
|
||||
Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
|
||||
---
|
||||
drivers/net/pfe_eth/pfe_eth.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
|
||||
index 528ede9..9a90b38 100644
|
||||
--- a/drivers/net/pfe_eth/pfe_eth.c
|
||||
+++ b/drivers/net/pfe_eth/pfe_eth.c
|
||||
@@ -329,7 +329,7 @@ struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info)
|
||||
|
||||
/*configure mdio speed */
|
||||
mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
|
||||
- mdio_speed |= EMAC_HOLDTIME(0x4);
|
||||
+ mdio_speed |= EMAC_HOLDTIME(0x5);
|
||||
writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
|
||||
|
||||
ret = mdio_register(bus);
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,65 +0,0 @@ |
||||
From f95f8ebd8d55ccc27e1615b251450915a1c14315 Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Tue, 12 Jul 2016 14:17:17 +0530
|
||||
Subject: [PATCH 74/93] board: freescale: ls1012a: Intergrate and enable PPA
|
||||
on LS1012AFRDM
|
||||
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012afrdm/ls1012afrdm.c | 9 +++++++++
|
||||
include/configs/ls1012afrdm.h | 12 ++++++++++++
|
||||
2 files changed, 21 insertions(+)
|
||||
|
||||
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
index 4b7902a..04f8f9a 100644
|
||||
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
@@ -143,6 +143,9 @@ int board_early_init_f(void)
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
+#ifdef CONFIG_FSL_LS_PPA
|
||||
+ u64 ppa_entry;
|
||||
+#endif
|
||||
/*
|
||||
* Set CCI-400 control override register to enable barrier
|
||||
* transaction
|
||||
@@ -157,6 +160,12 @@ int board_init(void)
|
||||
enable_layerscape_ns_access();
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_FSL_LS_PPA
|
||||
+ ppa_init_pre(&ppa_entry);
|
||||
+
|
||||
+ if (ppa_entry)
|
||||
+ ppa_init_entry((void *)ppa_entry);
|
||||
+#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 622c774..26e3640 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -9,6 +9,18 @@
|
||||
|
||||
#include "ls1012a_common.h"
|
||||
|
||||
+#ifndef CONFIG_SECURE_BOOT
|
||||
+#define CONFIG_FSL_LS_PPA
|
||||
+#if defined(CONFIG_FSL_LS_PPA)
|
||||
+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
+
|
||||
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
+#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
|
||||
+#endif
|
||||
+#endif
|
||||
+#endif
|
||||
+
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,28 +0,0 @@ |
||||
From d2effd68c77b4965d74ac2a6154d668e24a6dd9f Mon Sep 17 00:00:00 2001
|
||||
From: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
Date: Fri, 8 Jul 2016 16:01:31 +0800
|
||||
Subject: [PATCH 75/93] arm: ls1012ardb: add CONFIG_ARMV8_PSCI
|
||||
|
||||
[context adjustment]
|
||||
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
|
||||
---
|
||||
include/configs/ls1012ardb.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index fdaea3e..e97c1f9 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
#define CONFIG_FSL_LS_PPA
|
||||
#if defined(CONFIG_FSL_LS_PPA)
|
||||
+#define CONFIG_ARMV8_PSCI
|
||||
#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,25 +0,0 @@ |
||||
From ed6728fa22b4f09f6083d4c8b135f4b89487fee6 Mon Sep 17 00:00:00 2001
|
||||
From: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
Date: Wed, 13 Jul 2016 13:05:19 +0800
|
||||
Subject: [PATCH 76/93] arm: ls1012afrdm: add CONFIG_ARMV8_PSCI
|
||||
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
---
|
||||
include/configs/ls1012afrdm.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 26e3640..0e35fe9 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -12,6 +12,7 @@
|
||||
#ifndef CONFIG_SECURE_BOOT
|
||||
#define CONFIG_FSL_LS_PPA
|
||||
#if defined(CONFIG_FSL_LS_PPA)
|
||||
+#define CONFIG_ARMV8_PSCI
|
||||
#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,39 +0,0 @@ |
||||
From 2203e9045d8d113e1ecceddcbebcf78c66af557f Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Wed, 13 Jul 2016 15:49:12 +0530
|
||||
Subject: [PATCH 77/93] board: ls1012aqds: Avoid reset masking
|
||||
|
||||
FPGA regiser RST_MASK1 control reset masking for I2C, USB,
|
||||
Mem and EPHY1.
|
||||
|
||||
This register was being masked during initial debugging of
|
||||
RGMII. It is not required
|
||||
|
||||
So avoid masking of these device to send reset signals during
|
||||
soft-reset.
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012aqds/eth.c | 6 ------
|
||||
1 file changed, 6 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
|
||||
index 6fbbdbe..04d621c 100644
|
||||
--- a/board/freescale/ls1012aqds/eth.c
|
||||
+++ b/board/freescale/ls1012aqds/eth.c
|
||||
@@ -156,12 +156,6 @@ int board_eth_init(bd_t *bis)
|
||||
data8 |= 0x2;
|
||||
QIXIS_WRITE(rst_frc[0], data8);
|
||||
data8 = QIXIS_READ(rst_frc[0]);
|
||||
-
|
||||
- data8 = QIXIS_READ(res8[6]);
|
||||
- data8 |= 0xff;
|
||||
- QIXIS_WRITE(res8[6], data8);
|
||||
- data8 = QIXIS_READ(res8[6]);
|
||||
-
|
||||
#endif
|
||||
|
||||
mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,37 +0,0 @@ |
||||
From 50450fdcc39c3863351d52c290e77b664df33ed6 Mon Sep 17 00:00:00 2001
|
||||
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Date: Wed, 13 Jul 2016 15:49:22 +0530
|
||||
Subject: [PATCH 78/93] board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
|
||||
|
||||
~QIXIS_LBMAP_MASK is being used in code. So define inverse value
|
||||
LBMAP_MASK.
|
||||
|
||||
Aslo, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
|
||||
as 0b11 i.e. PORESET.
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
---
|
||||
include/configs/ls1012aqds.h | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
|
||||
index c06cfbd..418bd54 100644
|
||||
--- a/include/configs/ls1012aqds.h
|
||||
+++ b/include/configs/ls1012aqds.h
|
||||
@@ -89,11 +89,11 @@
|
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
#define QIXIS_LBMAP_BRDCFG_REG 0x04
|
||||
#define QIXIS_LBMAP_SWITCH 6
|
||||
-#define QIXIS_LBMAP_MASK 0xf7
|
||||
+#define QIXIS_LBMAP_MASK 0x08
|
||||
#define QIXIS_LBMAP_SHIFT 0
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x08
|
||||
-#define QIXIS_RST_CTL_RESET 0x41
|
||||
+#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,54 +0,0 @@ |
||||
From b43d6d42d734e78bd9b805a62f2a64933c144a41 Mon Sep 17 00:00:00 2001
|
||||
From: Sumit Garg <sumit.garg@nxp.com>
|
||||
Date: Thu, 14 Jul 2016 07:20:02 -0400
|
||||
Subject: [PATCH 80/93] ls1012ardb: PPA: Enable PPA validation in case of
|
||||
secure boot
|
||||
|
||||
As part of Secure Boot Chain of trust, enable validation of PPA image
|
||||
before the image is started.
|
||||
|
||||
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/fsl_secure_boot.h | 2 ++
|
||||
include/configs/ls1012a_common.h | 2 --
|
||||
include/configs/ls1012ardb.h | 2 ++
|
||||
3 files changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
|
||||
index b2e9105..0580fcd 100644
|
||||
--- a/arch/arm/include/asm/fsl_secure_boot.h
|
||||
+++ b/arch/arm/include/asm/fsl_secure_boot.h
|
||||
@@ -107,6 +107,8 @@
|
||||
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
|
||||
#ifdef CONFIG_LS1043A
|
||||
#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
|
||||
+#else
|
||||
+#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x40480000
|
||||
#endif
|
||||
#else
|
||||
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 0d64889..7e935ad 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -191,6 +191,4 @@
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
-#include <asm/fsl_secure_boot.h>
|
||||
-
|
||||
#endif /* __LS1012A_COMMON_H */
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index e97c1f9..d78edd2 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -149,4 +149,6 @@
|
||||
|
||||
#define CONFIG_FSL_CAAM /* Enable CAAM */
|
||||
|
||||
+#include <asm/fsl_secure_boot.h>
|
||||
+
|
||||
#endif /* __LS1012ARDB_H__ */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,79 +0,0 @@ |
||||
From 5d4a46fe8847d26112764c5768ff00f839fb3810 Mon Sep 17 00:00:00 2001
|
||||
From: Sumit Garg <sumit.garg@nxp.com>
|
||||
Date: Tue, 12 Jul 2016 14:05:34 -0400
|
||||
Subject: [PATCH 81/93] crypto/fsl: Update blob cmd to accept 64bit addresses
|
||||
|
||||
Update blob cmd to accept 64bit source, key modifier and destination
|
||||
addresses. Also correct output result print format for fsl specific
|
||||
implementation of blob cmd.
|
||||
|
||||
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
|
||||
---
|
||||
common/cmd_blob.c | 2 +-
|
||||
drivers/crypto/fsl/fsl_blob.c | 13 ++++++++++---
|
||||
2 files changed, 11 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/common/cmd_blob.c b/common/cmd_blob.c
|
||||
index ac8b268..bdd4cfd 100644
|
||||
--- a/common/cmd_blob.c
|
||||
+++ b/common/cmd_blob.c
|
||||
@@ -54,7 +54,7 @@ __weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
|
||||
*/
|
||||
static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
{
|
||||
- uint32_t key_addr, src_addr, dst_addr, len;
|
||||
+ ulong key_addr, src_addr, dst_addr, len;
|
||||
uint8_t *km_ptr, *src_ptr, *dst_ptr;
|
||||
int enc, ret = 0;
|
||||
|
||||
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
|
||||
index 8b25921..d24b8fc 100644
|
||||
--- a/drivers/crypto/fsl/fsl_blob.c
|
||||
+++ b/drivers/crypto/fsl/fsl_blob.c
|
||||
@@ -18,7 +18,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
|
||||
int ret, i = 0;
|
||||
u32 *desc;
|
||||
|
||||
- printf("\nDecapsulating data to form blob\n");
|
||||
+ printf("\nDecapsulating blob to get data\n");
|
||||
desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
|
||||
if (!desc) {
|
||||
debug("Not enough memory for descriptor allocation\n");
|
||||
@@ -27,12 +27,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
|
||||
|
||||
inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
|
||||
|
||||
+ debug("Descriptor dump:\n");
|
||||
for (i = 0; i < 14; i++)
|
||||
- printf("%x\n", *(desc + i));
|
||||
+ debug("Word[%d]: %08x\n", i, *(desc + i));
|
||||
ret = run_descriptor_jr(desc);
|
||||
|
||||
if (ret)
|
||||
printf("Error in Decapsulation %d\n", ret);
|
||||
+ else
|
||||
+ printf("Decapsulation Success\n");
|
||||
|
||||
free(desc);
|
||||
return ret;
|
||||
@@ -51,12 +54,16 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
|
||||
}
|
||||
|
||||
inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
|
||||
+
|
||||
+ debug("Descriptor dump:\n");
|
||||
for (i = 0; i < 14; i++)
|
||||
- printf("%x\n", *(desc + i));
|
||||
+ debug("Word[%d]: %08x\n", i, *(desc + i));
|
||||
ret = run_descriptor_jr(desc);
|
||||
|
||||
if (ret)
|
||||
printf("Error in Encapsulation %d\n", ret);
|
||||
+ else
|
||||
+ printf("Encapsulation Success\n");
|
||||
|
||||
free(desc);
|
||||
return ret;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,56 +0,0 @@ |
||||
From 9e157635c191762624c066d14e360e972aa1ad0f Mon Sep 17 00:00:00 2001
|
||||
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
|
||||
Date: Wed, 20 Jul 2016 15:44:58 +0800
|
||||
Subject: [PATCH 82/93] armv8: ls1012a: Update DDR timing
|
||||
|
||||
Update MMDC timing CL-tRCD-tRP to 7-7-7.
|
||||
|
||||
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
|
||||
---
|
||||
board/freescale/ls1012afrdm/ls1012afrdm.c | 2 +-
|
||||
board/freescale/ls1012aqds/ls1012aqds.c | 2 +-
|
||||
board/freescale/ls1012ardb/ls1012ardb.c | 2 +-
|
||||
3 files changed, 3 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
index 04f8f9a..a152a18 100644
|
||||
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
|
||||
@@ -55,7 +55,7 @@ void mmdc_init(void)
|
||||
/* configure timing parms */
|
||||
out_be32(&mmdc->mdotc, 0x12554000);
|
||||
out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
- out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
+ out_be32(&mmdc->mdcfg1, 0xdb328f64);
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
|
||||
/* other parms */
|
||||
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
index 4ae8def..7bdb591 100644
|
||||
--- a/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
|
||||
@@ -78,7 +78,7 @@ void mmdc_init(void)
|
||||
/* configure timing parms */
|
||||
out_be32(&mmdc->mdotc, 0x12554000);
|
||||
out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
- out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
+ out_be32(&mmdc->mdcfg1, 0xdb328f64);
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
|
||||
/* other parms */
|
||||
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
index 06e1f6b..ac51d56 100644
|
||||
--- a/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
|
||||
@@ -84,7 +84,7 @@ void mmdc_init(void)
|
||||
/* configure timing parms */
|
||||
out_be32(&mmdc->mdotc, 0x12554000);
|
||||
out_be32(&mmdc->mdcfg0, 0xbabf7954);
|
||||
- out_be32(&mmdc->mdcfg1, 0xff328f64);
|
||||
+ out_be32(&mmdc->mdcfg1, 0xdb328f64);
|
||||
out_be32(&mmdc->mdcfg2, 0x01ff00db);
|
||||
|
||||
/* other parms */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,120 +0,0 @@ |
||||
From db48271175c0566bb5e59776a23297d64aec9fcd Mon Sep 17 00:00:00 2001
|
||||
From: Alison Wang <b18965@freescale.com>
|
||||
Date: Thu, 21 Jul 2016 18:13:29 +0800
|
||||
Subject: [PATCH 83/93] armv8: fsl-layerscape: Fix the conflict between PPA
|
||||
and AArch32 support
|
||||
|
||||
As there is conflict between PPA and AArch32 support, this patch is to
|
||||
add a new defconfig for AArch32 support and move the definition for PPA
|
||||
to the board defconfig.
|
||||
|
||||
Signed-off-by: Alison Wang <alison.wang@nxp.com>
|
||||
---
|
||||
configs/ls1012afrdm_aarch32_qspi_defconfig | 11 +++++++++++
|
||||
configs/ls1012afrdm_qspi_defconfig | 1 +
|
||||
configs/ls1012ardb_aarch32_qspi_defconfig | 11 +++++++++++
|
||||
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 +
|
||||
configs/ls1012ardb_qspi_defconfig | 1 +
|
||||
include/configs/ls1012afrdm.h | 1 -
|
||||
include/configs/ls1012ardb.h | 1 -
|
||||
7 files changed, 25 insertions(+), 2 deletions(-)
|
||||
create mode 100644 configs/ls1012afrdm_aarch32_qspi_defconfig
|
||||
create mode 100644 configs/ls1012ardb_aarch32_qspi_defconfig
|
||||
|
||||
diff --git a/configs/ls1012afrdm_aarch32_qspi_defconfig b/configs/ls1012afrdm_aarch32_qspi_defconfig
|
||||
new file mode 100644
|
||||
index 0000000..1bb9080
|
||||
--- /dev/null
|
||||
+++ b/configs/ls1012afrdm_aarch32_qspi_defconfig
|
||||
@@ -0,0 +1,11 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TARGET_LS1012AFRDM=y
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
+# CONFIG_CMD_IMLS is not set
|
||||
+# CONFIG_FSL_LS_PPA is not set
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
|
||||
+CONFIG_OF_CONTROL=y
|
||||
+CONFIG_DM=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_DM_SPI=y
|
||||
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
|
||||
index e27181c..1f69db7 100644
|
||||
--- a/configs/ls1012afrdm_qspi_defconfig
|
||||
+++ b/configs/ls1012afrdm_qspi_defconfig
|
||||
@@ -2,6 +2,7 @@ CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012AFRDM=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
+CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
|
||||
CONFIG_OF_CONTROL=y
|
||||
diff --git a/configs/ls1012ardb_aarch32_qspi_defconfig b/configs/ls1012ardb_aarch32_qspi_defconfig
|
||||
new file mode 100644
|
||||
index 0000000..df16f3b
|
||||
--- /dev/null
|
||||
+++ b/configs/ls1012ardb_aarch32_qspi_defconfig
|
||||
@@ -0,0 +1,11 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TARGET_LS1012ARDB=y
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
+# CONFIG_CMD_IMLS is not set
|
||||
+# CONFIG_FSL_LS_PPA is not set
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
+CONFIG_OF_CONTROL=y
|
||||
+CONFIG_DM=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_DM_SPI=y
|
||||
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
index 92a95a8..4091503 100644
|
||||
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
@@ -2,6 +2,7 @@ CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012ARDB=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
+# CONFIG_FSL_LS_PPA is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
CONFIG_OF_CONTROL=y
|
||||
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
|
||||
index f819038..e025247 100644
|
||||
--- a/configs/ls1012ardb_qspi_defconfig
|
||||
+++ b/configs/ls1012ardb_qspi_defconfig
|
||||
@@ -2,6 +2,7 @@ CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012ARDB=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
+CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
CONFIG_OF_CONTROL=y
|
||||
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
|
||||
index 0e35fe9..a736687 100644
|
||||
--- a/include/configs/ls1012afrdm.h
|
||||
+++ b/include/configs/ls1012afrdm.h
|
||||
@@ -10,7 +10,6 @@
|
||||
#include "ls1012a_common.h"
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT
|
||||
-#define CONFIG_FSL_LS_PPA
|
||||
#if defined(CONFIG_FSL_LS_PPA)
|
||||
#define CONFIG_ARMV8_PSCI
|
||||
#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
|
||||
index d78edd2..400fa61 100644
|
||||
--- a/include/configs/ls1012ardb.h
|
||||
+++ b/include/configs/ls1012ardb.h
|
||||
@@ -9,7 +9,6 @@
|
||||
|
||||
#include "ls1012a_common.h"
|
||||
|
||||
-#define CONFIG_FSL_LS_PPA
|
||||
#if defined(CONFIG_FSL_LS_PPA)
|
||||
#define CONFIG_ARMV8_PSCI
|
||||
#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,43 +0,0 @@ |
||||
From 257802b8b8640e58e4a2001031f18facf056908e Mon Sep 17 00:00:00 2001
|
||||
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Date: Mon, 25 Jul 2016 16:41:24 +0530
|
||||
Subject: [PATCH 84/93] armv8: fsl-layerscape: Moving FSL_LS_PPA flag to
|
||||
EXTRA_OPTIONS
|
||||
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
---
|
||||
configs/ls1012afrdm_qspi_defconfig | 3 +--
|
||||
configs/ls1012ardb_qspi_defconfig | 3 +--
|
||||
2 files changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
|
||||
index 1f69db7..0d1b0f3 100644
|
||||
--- a/configs/ls1012afrdm_qspi_defconfig
|
||||
+++ b/configs/ls1012afrdm_qspi_defconfig
|
||||
@@ -1,8 +1,7 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012AFRDM=y
|
||||
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
-CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
|
||||
CONFIG_OF_CONTROL=y
|
||||
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
|
||||
index e025247..00e4dd2 100644
|
||||
--- a/configs/ls1012ardb_qspi_defconfig
|
||||
+++ b/configs/ls1012ardb_qspi_defconfig
|
||||
@@ -1,8 +1,7 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012ARDB=y
|
||||
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
-CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
CONFIG_OF_CONTROL=y
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,28 +0,0 @@ |
||||
From 0d3ccab8ba94f0cb1f5cb1c1391a79619c040f1c Mon Sep 17 00:00:00 2001
|
||||
From: Sumit Garg <sumit.garg@nxp.com>
|
||||
Date: Tue, 26 Jul 2016 07:43:41 -0400
|
||||
Subject: [PATCH 85/93] armv8: fsl-layerscape: Enable FSL_LS_PPA in Secure
|
||||
boot target
|
||||
|
||||
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
|
||||
---
|
||||
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 3 +--
|
||||
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
index 4091503..bb9099b 100644
|
||||
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
|
||||
@@ -1,8 +1,7 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012ARDB=y
|
||||
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA, SECURE_BOOT"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
-# CONFIG_FSL_LS_PPA is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
CONFIG_OF_CONTROL=y
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,233 +0,0 @@ |
||||
From 986172ece10eee928ce66597d76f3f40ac3d25f7 Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Mon, 8 Aug 2016 14:24:13 +0800
|
||||
Subject: [PATCH 86/93] driver: spi: add spansion s25fs-s family
|
||||
protect/unprotect
|
||||
|
||||
In order to support spansion s25fs512s flash protect/unprotect:
|
||||
|
||||
[1] Fill callbak flash->lock/unlock/is_locked by spansion_lock/
|
||||
unlock/is_locked.
|
||||
|
||||
[2] Achieve protect/unprotected by operating sr1nv, cr1nv.
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 194 +++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 194 insertions(+)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index e04bd55..87a92e9 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -877,6 +877,193 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
|
||||
}
|
||||
#endif
|
||||
|
||||
+#if defined(CONFIG_SPI_FLASH_SPANSION)
|
||||
+/*
|
||||
+ * Return 1 if the entire region is locked, 0 otherwise
|
||||
+ */
|
||||
+static int spansion_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
|
||||
+ u8 sr)
|
||||
+{
|
||||
+ loff_t lock_offs;
|
||||
+ u32 lock_len;
|
||||
+
|
||||
+ stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
|
||||
+
|
||||
+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Check if a region of the flash is (completely) locked. See spansion_lock() for
|
||||
+ * more info.
|
||||
+ *
|
||||
+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
|
||||
+ * negative on errors.
|
||||
+ */
|
||||
+int spansion_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
|
||||
+{
|
||||
+ u8 cmd[4];
|
||||
+ u32 sr1nv_offset = 0x0;
|
||||
+ u8 sr1nv;
|
||||
+ int ret;
|
||||
+
|
||||
+ cmd[0] = CMD_SPANSION_RDAR;
|
||||
+ cmd[1] = sr1nv_offset >> 16;
|
||||
+ cmd[2] = sr1nv_offset >> 8;
|
||||
+ cmd[3] = sr1nv_offset >> 0;
|
||||
+
|
||||
+ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
|
||||
+ if (ret)
|
||||
+ return -EIO;
|
||||
+
|
||||
+ return spansion_is_locked_sr(flash, ofs, len, sr1nv);
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Lock a region of the flash. Compatible with Spansion s25fs-s family flash.
|
||||
+ * Supports only the block protection bits BP{0,1,2} in the Status Register-1
|
||||
+ * Non-Volatile(SR1NV).
|
||||
+ *
|
||||
+ * Sample table portion for 64MB flash (S25FS512S):
|
||||
+ * Configuration Register-1 Non-Volatile(CR1NV[5])== 0
|
||||
+ *
|
||||
+ * | BP2 | BP1 | BP0 | Prot Length | Protected Portion
|
||||
+ * ------------------------------------------------------------
|
||||
+ * | 0 | 0 | 0 | NONE | NONE
|
||||
+ * | 0 | 0 | 1 | 1 MB | Upper 1/64
|
||||
+ * | 0 | 1 | 0 | 2 MB | Upper 1/32
|
||||
+ * | 0 | 1 | 1 | 4 MB | Upper 1/16
|
||||
+ * | 1 | 0 | 0 | 8 MB | Upper 1/8
|
||||
+ * | 1 | 0 | 1 | 16 MB | Upper 1/4
|
||||
+ * | 1 | 1 | 0 | 32 MB | Upper 1/2
|
||||
+ * | 1 | 1 | 1 | 64 MB | ALL
|
||||
+ *
|
||||
+ * When CR1NV[5] == 1, the Lower memory array are protected.
|
||||
+ *
|
||||
+ * Returns negative on errors, 0 on success.
|
||||
+ */
|
||||
+int spansion_lock(struct spi_flash *flash, u32 ofs, size_t len)
|
||||
+{
|
||||
+ u8 status_old, status_new;
|
||||
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
||||
+ u8 shift = ffs(mask) - 1, pow, val;
|
||||
+ int ret;
|
||||
+ u8 cmd[4];
|
||||
+ u32 sr1nv_offset = 0x0;
|
||||
+ u8 sr1nv;
|
||||
+
|
||||
+ cmd[0] = CMD_SPANSION_RDAR;
|
||||
+ cmd[1] = sr1nv_offset >> 16;
|
||||
+ cmd[2] = sr1nv_offset >> 8;
|
||||
+ cmd[3] = sr1nv_offset >> 0;
|
||||
+
|
||||
+ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
|
||||
+ if (ret)
|
||||
+ return -EIO;
|
||||
+ status_old = sr1nv;
|
||||
+
|
||||
+ /* SPI NOR always locks to the end */
|
||||
+ if (ofs + len != flash->size) {
|
||||
+ /* Does combined region extend to end? */
|
||||
+ if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
|
||||
+ status_old))
|
||||
+ return -EINVAL;
|
||||
+ len = flash->size - ofs;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Need smallest pow such that:
|
||||
+ *
|
||||
+ * 1 / (2^pow) <= (len / size)
|
||||
+ *
|
||||
+ * so (assuming power-of-2 size) we do:
|
||||
+ *
|
||||
+ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
|
||||
+ */
|
||||
+ pow = ilog2(flash->size) - ilog2(len);
|
||||
+ val = mask - (pow << shift);
|
||||
+ if (val & ~mask)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ /* Don't "lock" with no region! */
|
||||
+ if (!(val & mask))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ status_new = (status_old & ~mask) | val;
|
||||
+
|
||||
+ /* Only modify protection if it will not unlock other areas */
|
||||
+ if ((status_new & mask) <= (status_old & mask))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ cmd[0] = CMD_SPANSION_WRAR;
|
||||
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1);
|
||||
+ if (ret)
|
||||
+ return -EIO;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Unlock a region of the flash. See spansion_lock() for more info
|
||||
+ *
|
||||
+ * Returns negative on errors, 0 on success.
|
||||
+ */
|
||||
+int spansion_unlock(struct spi_flash *flash, u32 ofs, size_t len)
|
||||
+{
|
||||
+ uint8_t status_old, status_new;
|
||||
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
||||
+ u8 shift = ffs(mask) - 1, pow, val;
|
||||
+ int ret;
|
||||
+
|
||||
+ u8 cmd[4];
|
||||
+ u32 sr1nv_offset = 0x0;
|
||||
+ u8 sr1nv;
|
||||
+
|
||||
+ cmd[0] = CMD_SPANSION_RDAR;
|
||||
+ cmd[1] = sr1nv_offset >> 16;
|
||||
+ cmd[2] = sr1nv_offset >> 8;
|
||||
+ cmd[3] = sr1nv_offset >> 0;
|
||||
+
|
||||
+ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
|
||||
+ if (ret)
|
||||
+ return -EIO;
|
||||
+ status_old = sr1nv;
|
||||
+
|
||||
+ /* Cannot unlock; would unlock larger region than requested */
|
||||
+ if (spansion_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
|
||||
+ status_old))
|
||||
+ return -EINVAL;
|
||||
+ /*
|
||||
+ * Need largest pow such that:
|
||||
+ *
|
||||
+ * 1 / (2^pow) >= (len / size)
|
||||
+ *
|
||||
+ * so (assuming power-of-2 size) we do:
|
||||
+ *
|
||||
+ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
|
||||
+ */
|
||||
+ pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
|
||||
+ if (ofs + len == flash->size) {
|
||||
+ val = 0; /* fully unlocked */
|
||||
+ } else {
|
||||
+ val = mask - (pow << shift);
|
||||
+ /* Some power-of-two sizes are not supported */
|
||||
+ if (val & ~mask)
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ status_new = (status_old & ~mask) | val;
|
||||
+
|
||||
+ /* Only modify protection if it will not lock other areas */
|
||||
+ if ((status_new & mask) >= (status_old & mask))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ cmd[0] = CMD_SPANSION_WRAR;
|
||||
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1);
|
||||
+ if (ret)
|
||||
+ return -EIO;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_MACRONIX
|
||||
static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
|
||||
@@ -1132,6 +1319,13 @@ int spi_flash_scan(struct spi_flash *flash)
|
||||
flash->flash_is_locked = stm_is_locked;
|
||||
#endif
|
||||
break;
|
||||
+#if defined(CONFIG_SPI_FLASH_SPANSION)
|
||||
+ case SPI_FLASH_CFI_MFR_SPANSION:
|
||||
+ flash->flash_lock = spansion_lock;
|
||||
+ flash->flash_unlock = spansion_unlock;
|
||||
+ flash->flash_is_locked = spansion_is_locked;
|
||||
+#endif
|
||||
+ break;
|
||||
default:
|
||||
debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
|
||||
}
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,30 +0,0 @@ |
||||
From 5610e5d9a759ecf48eccc1271aea8f8bc3399b50 Mon Sep 17 00:00:00 2001
|
||||
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Date: Wed, 17 Aug 2016 18:31:53 +0530
|
||||
Subject: [PATCH 87/93] armv8/ls1012a: Update bootargs
|
||||
|
||||
Add optimization parameters like "quiet" in bootargs to reduce the system
|
||||
boot time
|
||||
|
||||
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
|
||||
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
|
||||
---
|
||||
include/configs/ls1012a_common.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 7e935ad..0489492 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -153,7 +153,7 @@
|
||||
#define CONFIG_BOOTCOMMAND "bootm $kernel_load"
|
||||
#else
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
|
||||
- "earlycon=uart8250,mmio,0x21c0500"
|
||||
+ "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
|
||||
#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
|
||||
"$kernel_start $kernel_size && "\
|
||||
"bootm $kernel_load"
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,31 +0,0 @@ |
||||
From b045189aef457833face5d7c4506e908289d2bfe Mon Sep 17 00:00:00 2001
|
||||
From: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
Date: Thu, 18 Aug 2016 11:24:46 +0800
|
||||
Subject: [PATCH 88/93] driver: spi: enable stm_get_locked_range() for
|
||||
spansion flash
|
||||
|
||||
stm_get_locked_range() is also applicable for spansion flash, So we can
|
||||
share it.
|
||||
|
||||
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index 87a92e9..d69d2c3 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -702,7 +702,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
|
||||
}
|
||||
#endif
|
||||
|
||||
-#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
|
||||
+#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) || \
|
||||
+ defined(CONFIG_SPI_FLASH_SPANSION)
|
||||
static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
|
||||
u32 *len)
|
||||
{
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,27 +0,0 @@ |
||||
From 17c9f2a306b56d5ec5e5c54ce9abba6926831c46 Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Fri, 23 Sep 2016 04:21:38 +0800
|
||||
Subject: [PATCH 89/93] driver: spi: fix id enclosure error
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi/spi_flash.c | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
|
||||
index d69d2c3..dcb1628 100644
|
||||
--- a/drivers/mtd/spi/spi_flash.c
|
||||
+++ b/drivers/mtd/spi/spi_flash.c
|
||||
@@ -1206,9 +1206,7 @@ int spi_flash_scan(struct spi_flash *flash)
|
||||
u8 idcode[5];
|
||||
u8 cmd;
|
||||
int ret;
|
||||
-#ifdef CONFIG_SPI_FLASH_SPANSION
|
||||
u8 id[6];
|
||||
-#endif
|
||||
|
||||
/* Read the ID codes */
|
||||
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,25 +0,0 @@ |
||||
From 0a8ebc8b855275b5fa035f33a964316d2b7b9a9e Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Fri, 23 Sep 2016 04:34:29 +0800
|
||||
Subject: [PATCH 90/93] ls1012: add CONFIG_SYS_FSL_MAX_NUM_OF_SEC define
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
index efaa79a..f1eb0d7 100644
|
||||
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
|
||||
@@ -246,6 +246,7 @@
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#else
|
||||
#error SoC not defined
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,47 +0,0 @@ |
||||
From da79bd42be7226c6db58b21b1fed595587d8dcaa Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Tue, 18 Oct 2016 18:44:23 +0800
|
||||
Subject: [PATCH 91/93] armv8: fsl-layerscape: ls1012ardb: configs: disable
|
||||
FSL_LS_PPA and remove aarch32 config
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
configs/ls1012ardb_aarch32_qspi_defconfig | 11 -----------
|
||||
configs/ls1012ardb_qspi_defconfig | 3 ++-
|
||||
2 files changed, 2 insertions(+), 12 deletions(-)
|
||||
delete mode 100644 configs/ls1012ardb_aarch32_qspi_defconfig
|
||||
|
||||
diff --git a/configs/ls1012ardb_aarch32_qspi_defconfig b/configs/ls1012ardb_aarch32_qspi_defconfig
|
||||
deleted file mode 100644
|
||||
index df16f3b..0000000
|
||||
--- a/configs/ls1012ardb_aarch32_qspi_defconfig
|
||||
+++ /dev/null
|
||||
@@ -1,11 +0,0 @@
|
||||
-CONFIG_ARM=y
|
||||
-CONFIG_TARGET_LS1012ARDB=y
|
||||
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
-# CONFIG_CMD_IMLS is not set
|
||||
-# CONFIG_FSL_LS_PPA is not set
|
||||
-CONFIG_SYS_NS16550=y
|
||||
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
-CONFIG_OF_CONTROL=y
|
||||
-CONFIG_DM=y
|
||||
-CONFIG_SPI_FLASH=y
|
||||
-CONFIG_DM_SPI=y
|
||||
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
|
||||
index 00e4dd2..df16f3b 100644
|
||||
--- a/configs/ls1012ardb_qspi_defconfig
|
||||
+++ b/configs/ls1012ardb_qspi_defconfig
|
||||
@@ -1,7 +1,8 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1012ARDB=y
|
||||
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
|
||||
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
+# CONFIG_FSL_LS_PPA is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
CONFIG_OF_CONTROL=y
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,67 +0,0 @@ |
||||
From b0f227f32f898bdf52f4ecafc83d1e2f1d6ee6ec Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Thu, 27 Oct 2016 23:47:43 +0800
|
||||
Subject: [PATCH 92/93] armv8: set openwrt/lede default boot env for
|
||||
ls1012ardb
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
include/configs/ls1012a_common.h | 28 +++++++++++++++++++++++++++-
|
||||
1 file changed, 27 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
|
||||
index 0489492..b23ba4f 100644
|
||||
--- a/include/configs/ls1012a_common.h
|
||||
+++ b/include/configs/ls1012a_common.h
|
||||
@@ -130,6 +130,24 @@
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
+#define WRTBOOT_DEFAULT "pfe stop && sf probe 0:0 && setenv bootargs " \
|
||||
+ "root=/dev/mtdblock5 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200 " \
|
||||
+ "earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1M(rcw)," \
|
||||
+ "1M(u-boot),1M(u-boot-env),1M(dtb),5M(kernel),23M(rootfs),32M(user)" \
|
||||
+ " && sf read $fdtaddr 0x300000 100000 && " \
|
||||
+ "sf read $loadaddr 0x400000 500000 && bootm $loadaddr - $fdtaddr"
|
||||
+
|
||||
+#define WRTBOOT_EXT4RFS "pfe stop && sf probe 0:0 && setenv bootargs " \
|
||||
+ "root=/dev/mtdblock5 rootfstype=ext4 noinitrd console=ttyS0,115200 " \
|
||||
+ "earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1M(rcw)," \
|
||||
+ "1M(u-boot),1M(u-boot-env),1M(dtb),5M(kernel),23M(ext4rfs),32M(user)" \
|
||||
+ " && sf read $fdtaddr 0x300000 100000 && " \
|
||||
+ "sf read $loadaddr 0x400000 500000 && bootm $loadaddr - $fdtaddr"
|
||||
+
|
||||
+#define WRTUPDATE_DEFAULT " sf probe 0:0 && tftp 0xa0000000 <tftp_folder>/" \
|
||||
+ "lede-layerscape-64b-ls1012ardb-squashfs-firmware.ext4.bin && protect off all" \
|
||||
+ " && sf erase 0 $filesize && sf write 0xa0000000 0 $filesize; reset"
|
||||
+
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
@@ -144,6 +162,12 @@
|
||||
"kernel_start=0xa00000\0" \
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
+ "loadaddr=82000000\0" \
|
||||
+ "ramdiskaddr=88000000\0" \
|
||||
+ "fdtaddr=8f000000\0" \
|
||||
+ "wrtboot=" WRTBOOT_DEFAULT "\0" \
|
||||
+ "wrtboot_ext4rfs=" WRTBOOT_EXT4RFS "\0" \
|
||||
+ "wrtupdate=" WRTUPDATE_DEFAULT "\0" \
|
||||
"console=ttyAMA0,38400n8\0"
|
||||
|
||||
#ifdef CONFIG_EMU
|
||||
@@ -158,7 +182,9 @@
|
||||
"$kernel_start $kernel_size && "\
|
||||
"bootm $kernel_load"
|
||||
#endif
|
||||
-#define CONFIG_BOOTDELAY 10
|
||||
+#define CONFIG_BOOTDELAY 3
|
||||
+#undef CONFIG_BOOTCOMMAND
|
||||
+#define CONFIG_BOOTCOMMAND "run wrtboot_ext4rfs"
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,70 +0,0 @@ |
||||
From f13ff4fe020c9018eb5a472b7c8a69a54e45ce29 Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Tue, 18 Oct 2016 22:37:17 +0800
|
||||
Subject: [PATCH 93/93] add byte_swap.tcl script for uboot can run/save in
|
||||
qspi flash
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
Makefile | 1 +
|
||||
byte_swap.tcl | 36 ++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 37 insertions(+)
|
||||
create mode 100755 byte_swap.tcl
|
||||
|
||||
diff --git a/Makefile b/Makefile
|
||||
index 1c2818c..b73375f 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -836,6 +836,7 @@ dtbs dts/dt.dtb: checkdtc u-boot
|
||||
|
||||
u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
|
||||
$(call if_changed,cat)
|
||||
+ tclsh byte_swap.tcl u-boot-dtb.bin u-boot-swap.bin 8
|
||||
|
||||
%.imx: %.bin
|
||||
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
|
||||
diff --git a/byte_swap.tcl b/byte_swap.tcl
|
||||
new file mode 100755
|
||||
index 0000000..a4e8008
|
||||
--- /dev/null
|
||||
+++ b/byte_swap.tcl
|
||||
@@ -0,0 +1,36 @@
|
||||
+puts $argv
|
||||
+set i_file [lindex $argv 0]
|
||||
+set o_file [lindex $argv 1]
|
||||
+set num_b [lindex $argv 2]
|
||||
+puts ""
|
||||
+
|
||||
+set fileid_i [open $i_file "r"]
|
||||
+set fileid_o [open $o_file "w+"]
|
||||
+fconfigure $fileid_i -translation {binary binary}
|
||||
+fconfigure $fileid_o -translation {binary binary}
|
||||
+
|
||||
+set old_bin [read $fileid_i]
|
||||
+set new_bin {}
|
||||
+set old_length [string length $old_bin]
|
||||
+set old_rem [expr $old_length % $num_b]
|
||||
+if {$old_rem != 0} {
|
||||
+ for {set i 0} {$i< [expr $num_b - $old_rem]} {incr i 1} {
|
||||
+ append old_bin y
|
||||
+ }
|
||||
+}
|
||||
+for {set i 0} {$i<[string length $old_bin]} {incr i $num_b} {
|
||||
+ for {set j $num_b} {$j>0} {incr j -1} {
|
||||
+ append new_bin [string index $old_bin [expr $i+($j-1)]]
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+for {set i 0} {$i<[string length $old_bin]} {incr i $num_b} {
|
||||
+ set binValue [string range $old_bin [expr $i+0] [expr $i+($num_b-1)]]
|
||||
+ binary scan $binValue H[expr $num_b*2] hexValue
|
||||
+
|
||||
+ set binValue [string range $new_bin [expr $i+0] [expr $i+($num_b-1)]]
|
||||
+ binary scan $binValue H[expr $num_b*2] hexValue
|
||||
+}
|
||||
+
|
||||
+puts -nonewline $fileid_o $new_bin
|
||||
+close $fileid_o
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -1,72 +0,0 @@ |
||||
From 61cf7655f6f165645d1659c7b256be4397d67572 Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Tue, 15 Nov 2016 20:57:37 +0800
|
||||
Subject: [PATCH 94/94] using perl script:byte_swap.pl to replace tcl
|
||||
script:byte_swap.tcl
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
Makefile | 2 +-
|
||||
byte_swap.pl | 37 +++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 38 insertions(+), 1 deletion(-)
|
||||
create mode 100755 byte_swap.pl
|
||||
|
||||
diff --git a/Makefile b/Makefile
|
||||
index b73375f..5293bc5 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -836,7 +836,7 @@ dtbs dts/dt.dtb: checkdtc u-boot
|
||||
|
||||
u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
|
||||
$(call if_changed,cat)
|
||||
- tclsh byte_swap.tcl u-boot-dtb.bin u-boot-swap.bin 8
|
||||
+ perl byte_swap.pl u-boot-dtb.bin u-boot-swap.bin 8
|
||||
|
||||
%.imx: %.bin
|
||||
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
|
||||
diff --git a/byte_swap.pl b/byte_swap.pl
|
||||
new file mode 100755
|
||||
index 0000000..1707139
|
||||
--- /dev/null
|
||||
+++ b/byte_swap.pl
|
||||
@@ -0,0 +1,37 @@
|
||||
+#!/usr/bin/perl
|
||||
+#
|
||||
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
|
||||
+#
|
||||
+# This is free software, licensed under the GNU General Public License v2.
|
||||
+# See /LICENSE for more information.
|
||||
+#
|
||||
+open F_I, '<', $ARGV[0] or die "Error:$!\n";
|
||||
+open F_O, '>', $ARGV[1] or die "Error:$!\n";
|
||||
+$i_size = (stat $ARGV[0])[7];
|
||||
+
|
||||
+undef $/;
|
||||
+$str_i=<F_I>;
|
||||
+(@ary_i)=unpack("C$i_size", $str_i);
|
||||
+
|
||||
+if ( ($i_size % $ARGV[2]) != 0 )
|
||||
+{
|
||||
+ for ($i=0; $i<$ARGV[2] - ($i_size % $ARGV[2]); $i++)
|
||||
+ {
|
||||
+ $ary_i[$i_size + $i]=0;
|
||||
+ }
|
||||
+ $i_size=$i_size + ($ARGV[2] - ($i_size % $ARGV[2]));
|
||||
+}
|
||||
+
|
||||
+for ($i=0; $i<$i_size; $i += $ARGV[2])
|
||||
+{
|
||||
+ for ($j=0; $j<$ARGV[2]; $j++)
|
||||
+ {
|
||||
+ $ary_o[$i+$j]=$ary_i[$i+$ARGV[2]-$j-1];
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+binmode F_O;
|
||||
+print(F_O pack("C$i_size", @ary_o));
|
||||
+
|
||||
+close F_I;
|
||||
+close F_O;
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
Loading…
Reference in new issue