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@ -26,8 +26,8 @@ static void ar71xx_pci_irq_dispatch(void) |
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{ |
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u32 pending; |
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pending = ar71xx_reset_rr(RESET_REG_PCI_INT_STATUS) & |
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ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE); |
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pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) & |
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); |
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if (pending & PCI_INT_DEV0) |
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do_IRQ(AR71XX_PCI_IRQ_DEV0); |
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@ -45,15 +45,15 @@ static void ar71xx_pci_irq_dispatch(void) |
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static void ar71xx_pci_irq_unmask(unsigned int irq) |
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{ |
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irq -= AR71XX_PCI_IRQ_BASE; |
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ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, |
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ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) | (1 << irq)); |
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, |
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq)); |
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} |
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static void ar71xx_pci_irq_mask(unsigned int irq) |
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{ |
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irq -= AR71XX_PCI_IRQ_BASE; |
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ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, |
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ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) & ~(1 << irq)); |
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, |
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq)); |
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} |
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static struct irq_chip ar71xx_pci_irq_chip = { |
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@ -72,8 +72,8 @@ static void __init ar71xx_pci_irq_init(void) |
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{ |
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int i; |
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ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, 0); |
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ar71xx_reset_wr(RESET_REG_PCI_INT_STATUS, 0); |
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0); |
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0); |
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for (i = AR71XX_PCI_IRQ_BASE; |
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i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { |
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@ -167,8 +167,8 @@ static void ar71xx_misc_irq_dispatch(void) |
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{ |
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u32 pending; |
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pending = ar71xx_reset_rr(RESET_REG_MISC_INT_STATUS) |
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& ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE); |
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pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) |
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& ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); |
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if (pending & MISC_INT_UART) |
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do_IRQ(AR71XX_MISC_IRQ_UART); |
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@ -201,15 +201,15 @@ static void ar71xx_misc_irq_dispatch(void) |
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static void ar71xx_misc_irq_unmask(unsigned int irq) |
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{ |
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irq -= AR71XX_MISC_IRQ_BASE; |
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ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE, |
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ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) | (1 << irq)); |
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, |
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq)); |
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} |
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static void ar71xx_misc_irq_mask(unsigned int irq) |
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{ |
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irq -= AR71XX_MISC_IRQ_BASE; |
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ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE, |
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ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) & ~(1 << irq)); |
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, |
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq)); |
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} |
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struct irq_chip ar71xx_misc_irq_chip = { |
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@ -228,8 +228,8 @@ static void __init ar71xx_misc_irq_init(void) |
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{ |
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int i; |
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ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE, 0); |
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ar71xx_reset_wr(RESET_REG_MISC_INT_STATUS, 0); |
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0); |
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0); |
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for (i = AR71XX_MISC_IRQ_BASE; |
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { |
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