ath9k: fix 5/10 mhz channel bandwidth issues

SVN-Revision: 29437
13 years ago · cdda13e194
parent aa63f0bef6
commit cdda13e194
2 changed files with 76 additions and 0 deletions
--- a/package/mac80211/patches/543-ath9k_fix_half_quarter_rx_latency.patch
+++ b/package/mac80211/patches/543-ath9k_fix_half_quarter_rx_latency.patch
@ -0,0 +1,32 @@
+--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -1006,16 +1006,26 @@ void ath9k_hw_init_global_settings(struc
+ 
+ 	if (IS_CHAN_HALF_RATE(chan)) {
+ 		eifs = 175;
+-		rx_lat *= 2;
+
+		if (!AR_SREV_9300_20_OR_LATER(ah))
+			rx_lat = 10;
+		else
+			rx_lat *= 2;
+
+ 		tx_lat *= 2;
+ 		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
+-		    tx_lat += 11;
+			tx_lat += 11;
+ 
+ 		slottime = 13;
+ 		sifstime = 32;
+ 	} else if (IS_CHAN_QUARTER_RATE(chan)) {
+ 		eifs = 340;
+-		rx_lat = (rx_lat * 4) - 1;
+
+		if (!AR_SREV_9300_20_OR_LATER(ah))
+			rx_lat = 20;
+		else
+			rx_lat = (rx_lat * 4) - 1;
+
+ 		tx_lat *= 4;
+ 		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
+ 		    tx_lat += 22;
--- a/package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch
+++ b/package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch
@ -0,0 +1,44 @@
+--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -1007,31 +1007,35 @@ void ath9k_hw_init_global_settings(struc
+ 	if (IS_CHAN_HALF_RATE(chan)) {
+ 		eifs = 175;
+ 
+-		if (!AR_SREV_9300_20_OR_LATER(ah))
+		if (!AR_SREV_9300_20_OR_LATER(ah)) {
+ 			rx_lat = 10;
+-		else
+			sifstime = 8;
+		} else {
+ 			rx_lat *= 2;
+			sifstime = 32;
+		}
+ 
+ 		tx_lat *= 2;
+ 		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
+ 			tx_lat += 11;
+ 
+ 		slottime = 13;
+-		sifstime = 32;
+ 	} else if (IS_CHAN_QUARTER_RATE(chan)) {
+ 		eifs = 340;
+ 
+-		if (!AR_SREV_9300_20_OR_LATER(ah))
+		if (!AR_SREV_9300_20_OR_LATER(ah)) {
+ 			rx_lat = 20;
+-		else
+			sifstime = 8;
+		} else {
+ 			rx_lat = (rx_lat * 4) - 1;
+			sifstime = 64;
+		}
+ 
+ 		tx_lat *= 4;
+ 		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
+ 		    tx_lat += 22;
+ 
+ 		slottime = 21;
+-		sifstime = 64;
+ 	} else {
+ 		if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
+ 			eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;