ath9k: fix issues with external reset on AR913x

An external reset patch for AR955x accidentally led to external reset
being issued twice on AR913x, once before the RTC reset and once after.
This may be causing some stability issues.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
master
Felix Fietkau 8 years ago
parent 6b524fe5b8
commit c9c68c7177
  1. 5
      package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch
  2. 2
      package/kernel/mac80211/patches/325-ath9k-fix-ath9k_hw_gpio_get-to-return-0-or-1-on-succ.patch
  3. 4
      package/kernel/mac80211/patches/542-ath9k_debugfs_diag.patch
  4. 8
      package/kernel/mac80211/patches/544-ath9k-ar933x-usb-hang-workaround.patch

@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
return true;
}
@@ -1356,24 +1373,23 @@ static bool ath9k_hw_set_reset(struct at
@@ -1356,24 +1373,24 @@ static bool ath9k_hw_set_reset(struct at
rst_flags |= AR_RTC_RC_MAC_COLD;
}
@ -115,7 +115,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
- REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
}
+ ath9k_hw_external_reset(ah, type);
+ if (!AR_SREV_9100(ah))
+ ath9k_hw_external_reset(ah, type);
+
+ if (AR_SREV_9300(ah) || AR_SREV_9580(ah))
+ REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);

@ -18,7 +18,7 @@ Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -2812,7 +2812,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah,
@@ -2813,7 +2813,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah,
WARN_ON(1);
}

@ -94,7 +94,7 @@
struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1837,6 +1837,20 @@ u32 ath9k_hw_get_tsf_offset(struct times
@@ -1838,6 +1838,20 @@ u32 ath9k_hw_get_tsf_offset(struct times
}
EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
@ -115,7 +115,7 @@
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
struct ath9k_hw_cal_data *caldata, bool fastcc)
{
@@ -2045,6 +2059,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
@@ -2046,6 +2060,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
ar9003_hw_disable_phy_restart(ah);
ath9k_hw_apply_gpio_override(ah);

@ -20,7 +20,7 @@
/******************/
/* Chip Revisions */
/******************/
@@ -1413,6 +1426,9 @@ static bool ath9k_hw_set_reset(struct at
@@ -1414,6 +1427,9 @@ static bool ath9k_hw_set_reset(struct at
udelay(50);
}
@ -30,7 +30,7 @@
return true;
}
@@ -1512,6 +1528,9 @@ static bool ath9k_hw_chip_reset(struct a
@@ -1513,6 +1529,9 @@ static bool ath9k_hw_chip_reset(struct a
ar9003_hw_internal_regulator_apply(ah);
ath9k_hw_init_pll(ah, chan);
@ -40,7 +40,7 @@
return true;
}
@@ -1815,8 +1834,14 @@ static int ath9k_hw_do_fastcc(struct ath
@@ -1816,8 +1835,14 @@ static int ath9k_hw_do_fastcc(struct ath
if (AR_SREV_9271(ah))
ar9002_hw_load_ani_reg(ah, chan);
@ -55,7 +55,7 @@
return -EINVAL;
}
@@ -2070,6 +2095,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
@@ -2071,6 +2096,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
ath9k_hw_set_radar_params(ah);
}

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