John Crispin
14 years ago
parent
7ab8489f82
commit
c7bb106433
@ -1,32 +0,0 @@ |
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menu "Configuration" |
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depends on PACKAGE_uboot-lantiq |
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|
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config UBOOT_TARGET |
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string "target" |
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default "easy50712_DDR166M" |
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help |
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The configuration reflects the settings for a dedicated board hardware. |
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Select for Danube evaluation board easy50712_DDR166M . |
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Select for AR9 evaluation board easy50812_DDR166M . |
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config UBOOT_RAMBOOT |
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bool "Enable RAM boot image" |
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help |
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Using the UART boot mode of the ROM code this image could be loaded to the RAM. |
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While executing the image in the RAM the functionality of the uboot image can be |
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tested first without touching the original flash. |
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Note: Be carefull, by saving the environment the flash will be modified. |
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The OWRT flash layout differs from the layout provided by Lantiq / Infineon. |
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config UBOOT_RAMBOOT_DDR_CONFIG |
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string "DDR configuration file" |
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default "easy50712_DDR166M.conf" |
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depends on UBOOT_RAMBOOT |
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help |
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The DDR configuration file should reflect the DDR memory device configuration . |
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It will be used to create a RAM boot image |
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Select for Danube evalution board easy50712_DDR166M.conf . |
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Select for AR9 evalution board easy50812.conf . |
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Select for arcadyan PSC RAM board arcadyan.conf . |
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endmenu |
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@ -1,622 +0,0 @@ |
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/* |
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* Memory sub-system initialization code for Danube board. |
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* Andre Messerschmidt |
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* Copyright (c) 2005 Infineon Technologies AG |
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* |
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* Based on Inca-IP code |
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/* History: |
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peng liu May 25, 2006, for PLL setting after reset, 05252006 |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/regdef.h> |
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#if 0 |
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#if defined(CONFIG_USE_DDR_RAM) |
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#if defined(CONFIG_USE_DDR_RAM_CFG_111M) |
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#include "ddr_settings_r111.h" |
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#define DDR111 |
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#elif defined(CONFIG_USE_DDR_RAM_CFG_166M) |
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#include "ddr_settings_r166.h" |
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#define DDR166 |
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#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M) |
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#include "ddr_settings_e111.h" |
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#define DDR111 |
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#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M) |
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#include "ddr_settings_e166.h" |
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#define DDR166 |
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#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400) |
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#include "ddr_settings_PROMOSDDR400.h" |
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#define DDR166 |
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#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166) |
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#include "ddr_settings_Samsung_166.h" |
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#define DDR166 |
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#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166) |
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#include "ddr_settings_psc_166.h" |
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#define DDR166 |
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#else |
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#warning "missing definition for ddr_settings.h, use default!" |
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#include "ddr_settings.h" |
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#endif |
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#endif /* CONFIG_USE_DDR_RAM */ |
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#else |
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#include "ddr_settings.h" |
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#define DDR166 |
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#endif |
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#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE) |
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#error "missing include of ddr_settings.h" |
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#endif |
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#define EBU_MODUL_BASE 0xBE105300 |
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#define EBU_CLC(value) 0x0000(value) |
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#define EBU_CON(value) 0x0010(value) |
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#define EBU_ADDSEL0(value) 0x0020(value) |
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#define EBU_ADDSEL1(value) 0x0024(value) |
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#define EBU_ADDSEL2(value) 0x0028(value) |
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#define EBU_ADDSEL3(value) 0x002C(value) |
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#define EBU_BUSCON0(value) 0x0060(value) |
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#define EBU_BUSCON1(value) 0x0064(value) |
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#define EBU_BUSCON2(value) 0x0068(value) |
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#define EBU_BUSCON3(value) 0x006C(value) |
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#define MC_MODUL_BASE 0xBF800000 |
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#define MC_ERRCAUSE(value) 0x0010(value) |
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#define MC_ERRADDR(value) 0x0020(value) |
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#define MC_CON(value) 0x0060(value) |
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#define MC_SRAM_ENABLE 0x00000004 |
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#define MC_SDRAM_ENABLE 0x00000002 |
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#define MC_DDRRAM_ENABLE 0x00000001 |
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#define MC_SDR_MODUL_BASE 0xBF800200 |
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#define MC_IOGP(value) 0x0000(value) |
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#define MC_CTRLENA(value) 0x0010(value) |
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#define MC_MRSCODE(value) 0x0020(value) |
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#define MC_CFGDW(value) 0x0030(value) |
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#define MC_CFGPB0(value) 0x0040(value) |
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#define MC_LATENCY(value) 0x0080(value) |
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#define MC_TREFRESH(value) 0x0090(value) |
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#define MC_SELFRFSH(value) 0x00A0(value) |
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#define MC_DDR_MODUL_BASE 0xBF801000 |
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#define MC_DC00(value) 0x0000(value) |
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#define MC_DC01(value) 0x0010(value) |
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#define MC_DC02(value) 0x0020(value) |
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#define MC_DC03(value) 0x0030(value) |
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#define MC_DC04(value) 0x0040(value) |
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#define MC_DC05(value) 0x0050(value) |
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#define MC_DC06(value) 0x0060(value) |
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#define MC_DC07(value) 0x0070(value) |
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#define MC_DC08(value) 0x0080(value) |
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#define MC_DC09(value) 0x0090(value) |
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#define MC_DC10(value) 0x00A0(value) |
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#define MC_DC11(value) 0x00B0(value) |
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#define MC_DC12(value) 0x00C0(value) |
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#define MC_DC13(value) 0x00D0(value) |
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#define MC_DC14(value) 0x00E0(value) |
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#define MC_DC15(value) 0x00F0(value) |
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#define MC_DC16(value) 0x0100(value) |
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#define MC_DC17(value) 0x0110(value) |
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#define MC_DC18(value) 0x0120(value) |
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#define MC_DC19(value) 0x0130(value) |
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#define MC_DC20(value) 0x0140(value) |
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#define MC_DC21(value) 0x0150(value) |
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#define MC_DC22(value) 0x0160(value) |
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#define MC_DC23(value) 0x0170(value) |
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#define MC_DC24(value) 0x0180(value) |
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#define MC_DC25(value) 0x0190(value) |
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#define MC_DC26(value) 0x01A0(value) |
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#define MC_DC27(value) 0x01B0(value) |
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#define MC_DC28(value) 0x01C0(value) |
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#define MC_DC29(value) 0x01D0(value) |
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#define MC_DC30(value) 0x01E0(value) |
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#define MC_DC31(value) 0x01F0(value) |
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#define MC_DC32(value) 0x0200(value) |
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#define MC_DC33(value) 0x0210(value) |
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#define MC_DC34(value) 0x0220(value) |
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#define MC_DC35(value) 0x0230(value) |
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#define MC_DC36(value) 0x0240(value) |
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#define MC_DC37(value) 0x0250(value) |
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#define MC_DC38(value) 0x0260(value) |
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#define MC_DC39(value) 0x0270(value) |
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#define MC_DC40(value) 0x0280(value) |
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#define MC_DC41(value) 0x0290(value) |
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#define MC_DC42(value) 0x02A0(value) |
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#define MC_DC43(value) 0x02B0(value) |
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#define MC_DC44(value) 0x02C0(value) |
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#define MC_DC45(value) 0x02D0(value) |
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#define MC_DC46(value) 0x02E0(value) |
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#define RCU_OFFSET 0xBF203000 |
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#define RCU_RST_REQ (RCU_OFFSET + 0x0010) |
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#define RCU_STS (RCU_OFFSET + 0x0014) |
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#define CGU_OFFSET 0xBF103000 |
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#define PLL0_CFG (CGU_OFFSET + 0x0004) |
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#define PLL1_CFG (CGU_OFFSET + 0x0008) |
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#define PLL2_CFG (CGU_OFFSET + 0x000C) |
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#define CGU_SYS (CGU_OFFSET + 0x0010) |
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#define CGU_UPDATE (CGU_OFFSET + 0x0014) |
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#define IF_CLK (CGU_OFFSET + 0x0018) |
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#define CGU_SMD (CGU_OFFSET + 0x0020) |
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#define CGU_CT1SR (CGU_OFFSET + 0x0028) |
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#define CGU_CT2SR (CGU_OFFSET + 0x002C) |
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#define CGU_PCMCR (CGU_OFFSET + 0x0030) |
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#define PCI_CR_PCI (CGU_OFFSET + 0x0034) |
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#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) |
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#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) |
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#define CLK_MEASURE (CGU_OFFSET + 0x003C) |
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//05252006 |
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#define pll0_35MHz_CONFIG 0x9D861059 |
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#define pll1_35MHz_CONFIG 0x1A260CD9 |
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#define pll2_35MHz_CONFIG 0x8000f1e5 |
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#define pll0_36MHz_CONFIG 0x1000125D |
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#define pll1_36MHz_CONFIG 0x1B1E0C99 |
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#define pll2_36MHz_CONFIG 0x8002f2a1 |
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//05252006 |
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//06063001-joelin disable the PCI CFRAME mask -start |
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/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. |
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But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. |
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The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. |
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The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. |
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*/ |
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#define PCI_CR_PR_OFFSET 0xBE105400 |
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#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) |
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#define PCI_CONFIG_SPACE 0xB7000000 |
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#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) |
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//06063001-joelin disable the PCI CFRAME mask -end |
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.set noreorder
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/* |
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* void ebu_init(void) |
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*/ |
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.globl ebu_init
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.ent ebu_init
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ebu_init: |
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#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \ |
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defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \ |
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defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \ |
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defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3) |
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li t1, EBU_MODUL_BASE |
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#if defined(CONFIG_EBU_ADDSEL0) |
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li t2, CONFIG_EBU_ADDSEL0 |
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sw t2, EBU_ADDSEL0(t1) |
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#endif |
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#if defined(CONFIG_EBU_ADDSEL1) |
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li t2, CONFIG_EBU_ADDSEL1 |
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sw t2, EBU_ADDSEL1(t1) |
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#endif |
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#if defined(CONFIG_EBU_ADDSEL2) |
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li t2, CONFIG_EBU_ADDSEL2 |
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sw t2, EBU_ADDSEL2(t1) |
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#endif |
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#if defined(CONFIG_EBU_ADDSEL3) |
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li t2, CONFIG_EBU_ADDSEL3 |
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sw t2, EBU_ADDSEL3(t1) |
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#endif |
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#if defined(CONFIG_EBU_BUSCON0) |
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li t2, CONFIG_EBU_BUSCON0 |
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sw t2, EBU_BUSCON0(t1) |
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#endif |
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#if defined(CONFIG_EBU_BUSCON1) |
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li t2, CONFIG_EBU_BUSCON1 |
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sw t2, EBU_BUSCON1(t1) |
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#endif |
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#if defined(CONFIG_EBU_BUSCON2) |
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li t2, CONFIG_EBU_BUSCON2 |
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sw t2, EBU_BUSCON2(t1) |
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#endif |
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#if defined(CONFIG_EBU_BUSCON3) |
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li t2, CONFIG_EBU_BUSCON3 |
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sw t2, EBU_BUSCON3(t1) |
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#endif |
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#endif |
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j ra |
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nop |
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.end ebu_init
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/* |
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* void cgu_init(long) |
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* |
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* a0 has the clock value |
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*/ |
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.globl cgu_init
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.ent cgu_init
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cgu_init: |
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li t2, CGU_SYS |
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lw t2,0(t2) |
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beq t2,a0,freq_up2date |
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nop |
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li t2, RCU_STS |
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lw t2, 0(t2) |
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and t2,0x00020000 |
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beq t2,0x00020000,boot_36MHZ |
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nop |
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//05252006 |
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li t1, PLL0_CFG |
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li t2, pll0_35MHz_CONFIG |
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sw t2,0(t1) |
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li t1, PLL1_CFG |
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li t2, pll1_35MHz_CONFIG |
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sw t2,0(t1) |
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li t1, PLL2_CFG |
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li t2, pll2_35MHz_CONFIG |
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sw t2,0(t1) |
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li t1, CGU_SYS |
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sw a0,0(t1) |
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li t1, RCU_RST_REQ |
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li t2, 0x40000008 |
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sw t2,0(t1) |
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b wait_reset |
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nop |
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boot_36MHZ: |
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li t1, PLL0_CFG |
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li t2, pll0_36MHz_CONFIG |
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sw t2,0(t1) |
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li t1, PLL1_CFG |
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li t2, pll1_36MHz_CONFIG |
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sw t2,0(t1) |
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li t1, PLL2_CFG |
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li t2, pll2_36MHz_CONFIG |
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sw t2,0(t1) |
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li t1, CGU_SYS |
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sw a0,0(t1) |
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li t1, RCU_RST_REQ |
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li t2, 0x40000008 |
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sw t2,0(t1) |
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//05252006 |
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wait_reset: |
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b wait_reset |
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nop |
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freq_up2date: |
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j ra |
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nop |
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.end cgu_init
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#ifndef CONFIG_USE_DDR_RAM |
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/* |
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* void sdram_init(long) |
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* |
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* a0 has the clock value |
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*/ |
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.globl sdram_init
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.ent sdram_init
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sdram_init: |
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/* SDRAM Initialization |
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*/ |
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li t1, MC_MODUL_BASE |
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/* Clear Error log registers */ |
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sw zero, MC_ERRCAUSE(t1) |
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sw zero, MC_ERRADDR(t1) |
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/* Enable SDRAM module in memory controller */ |
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li t3, MC_SDRAM_ENABLE |
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lw t2, MC_CON(t1) |
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or t3, t2, t3 |
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sw t3, MC_CON(t1) |
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li t1, MC_SDR_MODUL_BASE |
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/* disable the controller */ |
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li t2, 0 |
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sw t2, MC_CTRLENA(t1) |
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li t2, 0x822 |
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sw t2, MC_IOGP(t1) |
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li t2, 0x2 |
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sw t2, MC_CFGDW(t1) |
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/* Set CAS Latency */ |
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li t2, 0x00000020 |
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sw t2, MC_MRSCODE(t1) |
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/* Set CS0 to SDRAM parameters */ |
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li t2, 0x000014d8 |
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sw t2, MC_CFGPB0(t1) |
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/* Set SDRAM latency parameters */ |
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li t2, 0x00036325; /* BC PC100 */
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sw t2, MC_LATENCY(t1) |
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/* Set SDRAM refresh rate */ |
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li t2, 0x00000C30 |
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sw t2, MC_TREFRESH(t1) |
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/* Clear Power-down registers */ |
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sw zero, MC_SELFRFSH(t1) |
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/* Finally enable the controller */ |
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li t2, 1 |
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sw t2, MC_CTRLENA(t1) |
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j ra |
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nop |
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.end sdram_init
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#endif /* !CONFIG_USE_DDR_RAM */ |
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#ifdef CONFIG_USE_DDR_RAM |
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/* |
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* void ddrram_init(long) |
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* |
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* a0 has the clock value |
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*/ |
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.globl ddrram_init
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.ent ddrram_init
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ddrram_init: |
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/* DDR-DRAM Initialization |
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*/ |
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li t1, MC_MODUL_BASE |
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/* Clear Error log registers */ |
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sw zero, MC_ERRCAUSE(t1) |
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sw zero, MC_ERRADDR(t1) |
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/* Enable DDR module in memory controller */ |
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li t3, MC_DDRRAM_ENABLE |
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lw t2, MC_CON(t1) |
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or t3, t2, t3 |
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sw t3, MC_CON(t1) |
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li t1, MC_DDR_MODUL_BASE |
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/* Write configuration to DDR controller registers */ |
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li t2, MC_DC0_VALUE |
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sw t2, MC_DC00(t1) |
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li t2, MC_DC1_VALUE |
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sw t2, MC_DC01(t1) |
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li t2, MC_DC2_VALUE |
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sw t2, MC_DC02(t1) |
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li t2, MC_DC3_VALUE |
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sw t2, MC_DC03(t1) |
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li t2, MC_DC4_VALUE |
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sw t2, MC_DC04(t1) |
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li t2, MC_DC5_VALUE |
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sw t2, MC_DC05(t1) |
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li t2, MC_DC6_VALUE |
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sw t2, MC_DC06(t1) |
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li t2, MC_DC7_VALUE |
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sw t2, MC_DC07(t1) |
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li t2, MC_DC8_VALUE |
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sw t2, MC_DC08(t1) |
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li t2, MC_DC9_VALUE |
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sw t2, MC_DC09(t1) |
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li t2, MC_DC10_VALUE |
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sw t2, MC_DC10(t1) |
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li t2, MC_DC11_VALUE |
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sw t2, MC_DC11(t1) |
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li t2, MC_DC12_VALUE |
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sw t2, MC_DC12(t1) |
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li t2, MC_DC13_VALUE |
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sw t2, MC_DC13(t1) |
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li t2, MC_DC14_VALUE |
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sw t2, MC_DC14(t1) |
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li t2, MC_DC15_VALUE |
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sw t2, MC_DC15(t1) |
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li t2, MC_DC16_VALUE |
||||
sw t2, MC_DC16(t1) |
||||
|
||||
li t2, MC_DC17_VALUE |
||||
sw t2, MC_DC17(t1) |
||||
|
||||
li t2, MC_DC18_VALUE |
||||
sw t2, MC_DC18(t1) |
||||
|
||||
li t2, MC_DC19_VALUE |
||||
sw t2, MC_DC19(t1) |
||||
|
||||
li t2, MC_DC20_VALUE |
||||
sw t2, MC_DC20(t1) |
||||
|
||||
li t2, MC_DC21_VALUE |
||||
sw t2, MC_DC21(t1) |
||||
|
||||
li t2, MC_DC22_VALUE |
||||
sw t2, MC_DC22(t1) |
||||
|
||||
li t2, MC_DC23_VALUE |
||||
sw t2, MC_DC23(t1) |
||||
|
||||
li t2, MC_DC24_VALUE |
||||
sw t2, MC_DC24(t1) |
||||
|
||||
li t2, MC_DC25_VALUE |
||||
sw t2, MC_DC25(t1) |
||||
|
||||
li t2, MC_DC26_VALUE |
||||
sw t2, MC_DC26(t1) |
||||
|
||||
li t2, MC_DC27_VALUE |
||||
sw t2, MC_DC27(t1) |
||||
|
||||
li t2, MC_DC28_VALUE |
||||
sw t2, MC_DC28(t1) |
||||
|
||||
li t2, MC_DC29_VALUE |
||||
sw t2, MC_DC29(t1) |
||||
|
||||
li t2, MC_DC30_VALUE |
||||
sw t2, MC_DC30(t1) |
||||
|
||||
li t2, MC_DC31_VALUE |
||||
sw t2, MC_DC31(t1) |
||||
|
||||
li t2, MC_DC32_VALUE |
||||
sw t2, MC_DC32(t1) |
||||
|
||||
li t2, MC_DC33_VALUE |
||||
sw t2, MC_DC33(t1) |
||||
|
||||
li t2, MC_DC34_VALUE |
||||
sw t2, MC_DC34(t1) |
||||
|
||||
li t2, MC_DC35_VALUE |
||||
sw t2, MC_DC35(t1) |
||||
|
||||
li t2, MC_DC36_VALUE |
||||
sw t2, MC_DC36(t1) |
||||
|
||||
li t2, MC_DC37_VALUE |
||||
sw t2, MC_DC37(t1) |
||||
|
||||
li t2, MC_DC38_VALUE |
||||
sw t2, MC_DC38(t1) |
||||
|
||||
li t2, MC_DC39_VALUE |
||||
sw t2, MC_DC39(t1) |
||||
|
||||
li t2, MC_DC40_VALUE |
||||
sw t2, MC_DC40(t1) |
||||
|
||||
li t2, MC_DC41_VALUE |
||||
sw t2, MC_DC41(t1) |
||||
|
||||
li t2, MC_DC42_VALUE |
||||
sw t2, MC_DC42(t1) |
||||
|
||||
li t2, MC_DC43_VALUE |
||||
sw t2, MC_DC43(t1) |
||||
|
||||
li t2, MC_DC44_VALUE |
||||
sw t2, MC_DC44(t1) |
||||
|
||||
li t2, MC_DC45_VALUE |
||||
sw t2, MC_DC45(t1) |
||||
|
||||
li t2, MC_DC46_VALUE |
||||
sw t2, MC_DC46(t1) |
||||
|
||||
li t2, 0x00000100 |
||||
sw t2, MC_DC03(t1) |
||||
|
||||
j ra |
||||
nop |
||||
|
||||
.end ddrram_init
|
||||
#endif /* CONFIG_USE_DDR_RAM */ |
||||
|
||||
.globl lowlevel_init
|
||||
.ent lowlevel_init
|
||||
lowlevel_init: |
||||
/* EBU, CGU and SDRAM/DDR-RAM Initialization. |
||||
*/ |
||||
move t0, ra |
||||
/* We rely on the fact that non of the following ..._init() functions |
||||
* modify t0 |
||||
*/ |
||||
#if defined(CONFIG_SYS_EBU_BOOT) |
||||
#if defined(DDR166) |
||||
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ |
||||
li a0,0xe8 |
||||
#elif defined(DDR133) |
||||
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */ |
||||
li a0,0xe9 |
||||
#else /* defined(DDR111) */ |
||||
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */ |
||||
li a0,0xea |
||||
#endif |
||||
bal cgu_init |
||||
nop |
||||
#endif /* CONFIG_SYS_EBU_BOOT */ |
||||
|
||||
bal ebu_init |
||||
nop |
||||
|
||||
//06063001-joelin disable the PCI CFRAME mask-start |
||||
#ifdef DISABLE_CFRAME |
||||
li t1, PCI_CR_PCI //mw bf103034 80000000 |
||||
li t2, 0x80000000 |
||||
sw t2,0(t1) |
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 |
||||
li t2, 0x103 |
||||
sw t2,0(t1) |
||||
|
||||
li t1, CS_CFM //mw b700006c 0 |
||||
li t2, 0x00 |
||||
sw t2, 0(t1) |
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 |
||||
li t2, 0x1000103 |
||||
sw t2, 0(t1) |
||||
#endif |
||||
//06063001-joelin disable the PCI CFRAME mask-end |
||||
|
||||
#ifdef CONFIG_SYS_EBU_BOOT |
||||
#ifndef CONFIG_SYS_RAMBOOT |
||||
#ifdef CONFIG_USE_DDR_RAM |
||||
bal ddrram_init |
||||
nop |
||||
#else |
||||
bal sdram_init |
||||
nop |
||||
#endif |
||||
#endif /* CONFIG_SYS_RAMBOOT */ |
||||
#endif /* CONFIG_SYS_EBU_BOOT */ |
||||
|
||||
move ra, t0 |
||||
j ra |
||||
nop |
||||
|
||||
.end lowlevel_init
|
||||
@ -1,47 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
#COBJS := $(BOARD).o
|
||||
COBJS-y += arv752.o athrs26_phy.o
|
||||
|
||||
SOBJS = lowlevel_init.o pmuenable.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,325 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2010 |
||||
* Thomas Langer, Ralph Hempel |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <netdev.h> |
||||
#include <miiphy.h> |
||||
#include <asm/addrspace.h> |
||||
#include <asm/danube.h> |
||||
#include <asm/reboot.h> |
||||
#include <asm/io.h> |
||||
#if defined(CONFIG_CMD_HTTPD) |
||||
#include <httpd.h> |
||||
#endif |
||||
#if defined(CONFIG_PCI) |
||||
#include <pci.h> |
||||
#endif |
||||
#include "athrs26_phy.h" |
||||
|
||||
extern ulong ifx_get_ddr_hz(void); |
||||
extern ulong ifx_get_cpuclk(void); |
||||
|
||||
/* IDs and registers of known external switches */ |
||||
void _machine_restart(void) |
||||
{ |
||||
*DANUBE_RCU_RST_REQ |=1<<30; |
||||
} |
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT |
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM); |
||||
} |
||||
#elif defined(CONFIG_USE_DDR_RAM) |
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
return (CONFIG_SYS_MAX_RAM); |
||||
} |
||||
#else |
||||
|
||||
static ulong max_sdram_size(void) /* per Chip Select */ |
||||
{ |
||||
/* The only supported SDRAM data width is 16bit.
|
||||
*/ |
||||
#define CFG_DW 4 |
||||
|
||||
/* The only supported number of SDRAM banks is 4.
|
||||
*/ |
||||
#define CFG_NB 4 |
||||
|
||||
ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0; |
||||
int cols = cfgpb0 & 0xF; |
||||
int rows = (cfgpb0 & 0xF0) >> 4; |
||||
ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines |
||||
* the actually available RAM size between addresses `base' and |
||||
* `base + maxsize'. |
||||
*/ |
||||
|
||||
static long int dram_size(long int *base, long int maxsize) |
||||
{ |
||||
volatile long int *addr; |
||||
ulong cnt, val; |
||||
ulong save[32]; /* to make test non-destructive */ |
||||
unsigned char i = 0; |
||||
|
||||
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
save[i++] = *addr; |
||||
*addr = ~cnt; |
||||
} |
||||
|
||||
/* write 0 to base address */ |
||||
addr = base; |
||||
save[i] = *addr; |
||||
*addr = 0; |
||||
|
||||
/* check at base address */ |
||||
if ((val = *addr) != 0) { |
||||
*addr = save[i]; |
||||
return (0); |
||||
} |
||||
|
||||
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
val = *addr; |
||||
*addr = save[--i]; |
||||
|
||||
if (val != (~cnt)) { |
||||
return (cnt * sizeof (long)); |
||||
} |
||||
} |
||||
return (maxsize); |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0; |
||||
ulong size, max_size = 0; |
||||
ulong our_address; |
||||
|
||||
/* load t9 into our_address */ |
||||
asm volatile ("move %0, $25" : "=r" (our_address) :); |
||||
|
||||
/* Can't probe for RAM size unless we are running from Flash.
|
||||
* find out whether running from DRAM or Flash. |
||||
*/ |
||||
if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) |
||||
{ |
||||
return max_sdram_size(); |
||||
} |
||||
|
||||
for (cols = 0x8; cols <= 0xC; cols++) |
||||
{ |
||||
for (rows = 0xB; rows <= 0xD; rows++) |
||||
{ |
||||
*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) | |
||||
(rows << 4) | cols; |
||||
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
||||
max_sdram_size()); |
||||
|
||||
if (size > max_size) |
||||
{ |
||||
best_val = *DANUBE_SDRAM_MC_CFGPB0; |
||||
max_size = size; |
||||
} |
||||
} |
||||
} |
||||
|
||||
*DANUBE_SDRAM_MC_CFGPB0 = best_val; |
||||
return max_size; |
||||
} |
||||
#endif |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
unsigned long chipid = *DANUBE_MPS_CHIPID; |
||||
int part_num; |
||||
|
||||
puts ("Board: ARV75DW22 - Easybox 803\n"); |
||||
puts ("SoC: "); |
||||
|
||||
part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid); |
||||
switch (part_num) |
||||
{ |
||||
case 0x129: |
||||
case 0x12D: |
||||
case 0x12b:
|
||||
puts("Danube/Twinpass/Vinax-VE "); |
||||
break; |
||||
default: |
||||
printf ("unknown, chip part number 0x%03X ", part_num); |
||||
break; |
||||
} |
||||
printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid)); |
||||
|
||||
printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000); |
||||
printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
||||
int board_early_init_f(void) |
||||
{ |
||||
#ifdef CONFIG_EBU_ADDSEL0 |
||||
(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0; |
||||
#endif |
||||
#ifdef CONFIG_EBU_ADDSEL1 |
||||
(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1; |
||||
#endif |
||||
#ifdef CONFIG_EBU_ADDSEL2 |
||||
(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2; |
||||
#endif |
||||
#ifdef CONFIG_EBU_ADDSEL3 |
||||
(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3; |
||||
#endif |
||||
#ifdef CONFIG_EBU_BUSCON0 |
||||
(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0; |
||||
#endif |
||||
#ifdef CONFIG_EBU_BUSCON1 |
||||
(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1; |
||||
#endif |
||||
#ifdef CONFIG_EBU_BUSCON2 |
||||
(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2; |
||||
#endif |
||||
#ifdef CONFIG_EBU_BUSCON3 |
||||
(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3; |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
||||
|
||||
|
||||
#ifdef CONFIG_EXTRA_SWITCH |
||||
static int external_switch_init(void) |
||||
{ |
||||
// switch reset pin on arv752
|
||||
*DANUBE_GPIO_P1_ALTSEL0 &= ~8; |
||||
*DANUBE_GPIO_P1_ALTSEL1 &= ~8; |
||||
*DANUBE_GPIO_P1_OD |= 8; |
||||
*DANUBE_GPIO_P1_DIR |= 8; |
||||
*DANUBE_GPIO_P1_OUT |= 8; |
||||
|
||||
puts("initializing ar8216 switch... "); |
||||
if (athrs26_phy_setup(0)==0) { |
||||
printf("initialized\n"); |
||||
return 0; |
||||
} |
||||
puts("failed ... \n"); |
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_EXTRA_SWITCH */ |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#if defined(CONFIG_IFX_ETOP) |
||||
uchar enetaddr[6]; |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016); |
||||
|
||||
*DANUBE_PMU_PWDCR &= 0xFFFFEFDF; |
||||
*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/ |
||||
|
||||
if (lq_eth_initialize(bis)) |
||||
return -1; |
||||
|
||||
*DANUBE_RCU_RST_REQ |=1; |
||||
udelay(200000); |
||||
*DANUBE_RCU_RST_REQ &=(unsigned long)~1; |
||||
udelay(1000); |
||||
|
||||
#ifdef CONFIG_EXTRA_SWITCH |
||||
if (external_switch_init()<0) |
||||
return -1; |
||||
#endif /* CONFIG_EXTRA_SWITCH */ |
||||
#endif /* CONFIG_IFX_ETOP */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_CMD_HTTPD) |
||||
int do_http_upgrade(const unsigned char *data, const ulong size) |
||||
{ |
||||
char buf[128]; |
||||
|
||||
if(getenv ("ram_addr") == NULL) |
||||
return -1; |
||||
if(getenv ("kernel_addr") == NULL) |
||||
return -1; |
||||
/* check the image */ |
||||
if(run_command("imi ${ram_addr}", 0) < 0) { |
||||
return -1; |
||||
} |
||||
/* write the image to the flash */ |
||||
puts("http ugrade ...\n"); |
||||
sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size); |
||||
return run_command(buf, 0); |
||||
} |
||||
|
||||
int do_http_progress(const int state) |
||||
{ |
||||
/* toggle LED's here */ |
||||
switch(state) { |
||||
case HTTP_PROGRESS_START: |
||||
puts("http start\n"); |
||||
break; |
||||
case HTTP_PROGRESS_TIMEOUT: |
||||
puts("."); |
||||
break; |
||||
case HTTP_PROGRESS_UPLOAD_READY: |
||||
puts("http upload ready\n"); |
||||
break; |
||||
case HTTP_PROGRESS_UGRADE_READY: |
||||
puts("http ugrade ready\n"); |
||||
break; |
||||
case HTTP_PROGRESS_UGRADE_FAILED: |
||||
puts("http ugrade failed\n"); |
||||
break; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
unsigned long do_http_tmp_address(void) |
||||
{ |
||||
char *s = getenv ("ram_addr"); |
||||
if (s) { |
||||
ulong tmp = simple_strtoul (s, NULL, 16); |
||||
return tmp; |
||||
} |
||||
return 0 /*0x80a00000*/; |
||||
} |
||||
|
||||
#endif |
||||
@ -1,60 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Danube board with MIPS 24Kc CPU core
|
||||
#
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp |
||||
|
||||
ifdef CONFIG_LZMA_BOOTSTRAP |
||||
|
||||
ifdef BUILD_BOOTSTRAP |
||||
|
||||
$(info BUILD_BOOTSTRAP ) |
||||
#TEXT_BASE = 0xB0000000
|
||||
TEXT_BASE = 0x80010000
|
||||
|
||||
else # BUILD_BOOTSTRAP
|
||||
|
||||
ifndef TEXT_BASE |
||||
$(info redefine TEXT_BASE = 0x80040000 ) |
||||
TEXT_BASE = 0x80040000
|
||||
endif |
||||
|
||||
endif # BUILD_BOOTSTRAP
|
||||
|
||||
else |
||||
|
||||
ifdef BUILD_BOOTSTRAP |
||||
$(error BUILD_BOOTSTRAP but not enabled in config) |
||||
endif |
||||
|
||||
ifndef TEXT_BASE |
||||
## Standard: boot from ebu
|
||||
$(info redefine TEXT_BASE = 0xB0000000 ) |
||||
TEXT_BASE = 0xB0000000
|
||||
## For testing: boot from RAM
|
||||
# TEXT_BASE = 0x80100000
|
||||
endif |
||||
|
||||
endif # CONFIG_LZMA_BOOTSTRAP
|
||||
@ -1,48 +0,0 @@ |
||||
/* |
||||
* Power Management unit initialization code for AMAZON development board. |
||||
* |
||||
* Copyright (c) 2003 Ou Ke, Infineon. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/regdef.h> |
||||
|
||||
#define PMU_PWDCR 0xBF10201C |
||||
#define PMU_SR 0xBF102020 |
||||
|
||||
.globl pmuenable
|
||||
|
||||
pmuenable: |
||||
li t0, PMU_PWDCR |
||||
li t1, 0x2 /* enable everything */ |
||||
sw t1, 0(t0) |
||||
#if 0 |
||||
1: |
||||
li t0, PMU_SR |
||||
lw t2, 0(t0) |
||||
bne t1, t2, 1b |
||||
nop |
||||
#endif |
||||
j ra |
||||
nop |
||||
|
||||
|
||||
@ -1,70 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk Engineering, <wd@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* |
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") |
||||
*/ |
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") |
||||
OUTPUT_ARCH(mips) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = .; |
||||
_gp = ALIGN(16) + 0x7ff0; |
||||
|
||||
.got : { |
||||
__got_start = .; |
||||
*(.got) |
||||
__got_end = .; |
||||
} |
||||
|
||||
.sdata : { *(.sdata) } |
||||
|
||||
.u_boot_cmd : { |
||||
__u_boot_cmd_start = .; |
||||
*(.u_boot_cmd) |
||||
__u_boot_cmd_end = .; |
||||
} |
||||
|
||||
uboot_end_data = .; |
||||
num_got_entries = (__got_end - __got_start) >> 2; |
||||
|
||||
. = ALIGN(4); |
||||
.sbss (NOLOAD) : { *(.sbss) } |
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } |
||||
uboot_end = .; |
||||
} |
||||
@ -0,0 +1,14 @@ |
||||
#ifndef __CONFIG_H_452C |
||||
#define __CONFIG_H_452C |
||||
|
||||
#define CONFIG_ARV4518 1 |
||||
#define CONFIG_ARCADYAN "ARV452CPW" |
||||
|
||||
#define CONFIG_SYS_MAX_RAM 32*1024*1024 |
||||
#define CONFIG_SYS_PROMPT "ARV452c => " |
||||
#define CONFIG_RMII 1 |
||||
#define CONFIG_RTL8306_SWITCH 1 |
||||
|
||||
#include "arcadyan-common.h" |
||||
|
||||
#endif |
||||
@ -0,0 +1,20 @@ |
||||
#ifndef __CONFIG_H_752DPW |
||||
#define __CONFIG_H_752DPW |
||||
|
||||
#define CONFIG_ARV752DPW 1 |
||||
#define CONFIG_ARCADYAN "ARV752DPW" |
||||
|
||||
#define CONFIG_SYS_MAX_RAM 64*1024*1024 |
||||
#define CONFIG_SYS_PROMPT "ARV752DPW => " |
||||
|
||||
//#define CONFIG_RMII
|
||||
#define CONFIG_RTL8306_SWITCH 1 |
||||
//#define CONFIG_EBU_GPIO 0x2
|
||||
#define CONFIG_SWITCH_PORT1 |
||||
#define CONFIG_SWITCH_PIN 3 |
||||
//#define CONFIG_BUTTON_PORT0
|
||||
//#define CONFIG_BUTTON_PIN 12
|
||||
|
||||
#include "arcadyan-common.h" |
||||
|
||||
#endif |
||||
@ -0,0 +1,20 @@ |
||||
#ifndef __CONFIG_H_752DPW22 |
||||
#define __CONFIG_H_752DPW22 |
||||
|
||||
#define CONFIG_ARV752DPW22 1 |
||||
#define CONFIG_ARCADYAN "ARV752DPW22" |
||||
|
||||
#define CONFIG_SYS_MAX_RAM 64*1024*1024 |
||||
#define CONFIG_SYS_PROMPT "ARV752DPW22 => " |
||||
|
||||
#define CONFIG_AR8216_SWITCH 1 |
||||
#define CONFIG_EBU_GPIO 0x2 |
||||
#define CONFIG_SWITCH_PORT1 |
||||
#define CONFIG_SWITCH_PIN 3 |
||||
#define CONFIG_BUTTON_PORT0 |
||||
#define CONFIG_BUTTON_PIN 13 |
||||
#define CONFIG_BUTTON_LEVEL 0 |
||||
|
||||
#include "arcadyan-common.h" |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue