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@ -151,7 +151,7 @@ void rb500_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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} |
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static struct resource nand_slot0_res[] = { |
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{ |
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[0] = { |
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.name = "nand_membase", |
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.flags = IORESOURCE_MEM |
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} |
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@ -163,8 +163,8 @@ struct platform_nand_data rb500_nand_data = { |
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}; |
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static struct platform_device nand_slot0 = { |
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.id = 0, |
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.name = "gen_nand", |
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.id = -1, |
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.resource = nand_slot0_res, |
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.num_resources = ARRAY_SIZE(nand_slot0_res), |
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.dev.platform_data = &rb500_nand_data, |
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@ -234,6 +234,13 @@ static void __init rb500_nand_setup(void) |
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changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX); |
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else |
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changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE); |
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/* Setup NAND specific settings */ |
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rb500_nand_data.chip.nr_chips = 1; |
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rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info); |
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rb500_nand_data.chip.partitions = rb500_partition_info; |
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rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY; |
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rb500_nand_data.chip.options = NAND_NO_AUTOINCR; |
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} |
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@ -248,19 +255,12 @@ static int __init plat_setup_devices(void) |
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cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; |
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} |
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/* Initialise the NAND device */ |
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rb500_nand_setup(); |
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/* Read the NAND resources from the device controller */ |
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nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE); |
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nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; |
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/* Setup NAND specific settings */ |
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rb500_nand_data.chip.nr_chips = 1; |
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rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info); |
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rb500_nand_data.chip.partitions = rb500_partition_info; |
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rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY; |
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rb500_nand_data.chip.options = NAND_NO_AUTOINCR; |
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/* Initialise the NAND device */ |
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rb500_nand_setup(); |
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return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs)); |
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} |
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