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@ -92,7 +92,7 @@ diff -Nur linux-2.6.15/arch/mips/aruba/idtIRQ.S linux-2.6.15-openwrt/arch/mips/a |
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diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c
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--- linux-2.6.15/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100
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@@ -0,0 +1,393 @@
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@@ -0,0 +1,424 @@
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+/**************************************************************************
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+ *
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+ * BRIEF MODULE DESCRIPTION
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@ -242,9 +242,14 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub |
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+
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+static void aruba_enable_irq(unsigned int irq_nr)
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+{
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+ unsigned long flags;
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int group, intr_bit;
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+ volatile unsigned int *addr;
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+
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+
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+ local_irq_save(flags);
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+
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+ if (ip < 0) {
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+ enable_local_irq(irq_nr);
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+ } else {
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@ -281,57 +286,70 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub |
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+ break;
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+ }
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+ }
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+
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+ local_irq_restore(flags);
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+
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+}
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+
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+static void aruba_disable_irq(unsigned int irq_nr)
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+{
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+ unsigned long flags;
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int group, intr_bit, mask;
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+ volatile unsigned int *addr;
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+
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+ // calculate group
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ group = ip >> 5;
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ group = 0;
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+ break;
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+ }
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+ local_irq_save(flags);
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+
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+ // calc interrupt bit within group
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+ ip -= group << 5;
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+ intr_bit = 1 << ip;
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+ if (ip < 0) {
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+ disable_local_irq(irq_nr);
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+ } else {
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+ // calculate group
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ group = ip >> 5;
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ group = 0;
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+ break;
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+ }
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ addr = intr_group_muscat[group].base_addr;
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+ // mask intr within group
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+ mask = READ_MASK_MUSCAT(addr);
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+ mask |= intr_bit;
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+ WRITE_MASK_MUSCAT(addr, mask);
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+ // calc interrupt bit within group
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+ ip -= group << 5;
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+ intr_bit = 1 << ip;
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ addr = intr_group_muscat[group].base_addr;
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+ // mask intr within group
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+ mask = READ_MASK_MUSCAT(addr);
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+ mask |= intr_bit;
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+ WRITE_MASK_MUSCAT(addr, mask);
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+
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+ /*
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+ if there are no more interrupts enabled in this
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+ group, disable corresponding IP
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+ */
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+ if (mask == intr_group_muscat[group].mask)
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+ disable_local_irq(group_to_ip(group));
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ addr = intr_group_merlot[group].base_addr;
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+ // mask intr within group
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+ mask = READ_MASK_MERLOT(addr);
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+ mask &= ~intr_bit;
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+ WRITE_MASK_MERLOT(addr, mask);
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+ if (!mask)
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+ disable_local_irq(group_to_ip(group));
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+ break;
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+ /*
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+ if there are no more interrupts enabled in this
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+ group, disable corresponding IP
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+ */
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+ if (mask == intr_group_muscat[group].mask)
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+ disable_local_irq(group_to_ip(group));
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ addr = intr_group_merlot[group].base_addr;
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+ // mask intr within group
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+ mask = READ_MASK_MERLOT(addr);
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+ mask &= ~intr_bit;
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+ WRITE_MASK_MERLOT(addr, mask);
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+ if (!mask)
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+ disable_local_irq(group_to_ip(group));
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+ break;
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+ }
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+ }
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+
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+ local_irq_restore(flags);
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+
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+}
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+
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+static unsigned int startup_irq(unsigned int irq_nr)
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@ -355,50 +373,60 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub |
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+static void end_irq(unsigned int irq_nr)
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+{
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+
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+ unsigned long flags;
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int intr_bit, group;
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+ volatile unsigned int *addr;
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+
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+
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+ local_irq_save(flags);
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+ if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
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+ printk("warning: end_irq %d did not enable (%x)\n",
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+ printk("warning: end_irq %d did not enable (%x) (ignoring)\n",
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+ irq_nr, irq_desc[irq_nr].status);
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+ }
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
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+
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+ group = ip >> 5;
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+ if (ip<0) {
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+ enable_local_irq(irq_nr);
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+ } else {
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
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+
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+ group = ip >> 5;
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+
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+ // calc interrupt bit within group
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+ ip -= (group << 5);
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+ intr_bit = 1 << ip;
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+
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+
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+ addr = intr_group_muscat[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ group = 0;
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+
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+ // calc interrupt bit within group
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+ ip -= (group << 5);
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+ intr_bit = 1 << ip;
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+ // calc interrupt bit within group
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+ intr_bit = 1 << ip;
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+
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+
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+ addr = intr_group_muscat[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ group = 0;
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+
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+ // calc interrupt bit within group
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+ intr_bit = 1 << ip;
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+
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+
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+ addr = intr_group_merlot[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
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+ break;
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+ addr = intr_group_merlot[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
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+ break;
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+ }
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+ }
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+ local_irq_restore(flags);
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+}
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+
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+static struct hw_interrupt_type aruba_irq_type = {
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@ -418,6 +446,9 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub |
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+ memset(irq_desc, 0, sizeof(irq_desc));
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+ set_except_vector(0, idtIRQ);
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+
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+
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+ set_c0_status(0xFF00);
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+
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+ for (i = 0; i < RC32434_NR_IRQS; i++) {
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+ irq_desc[i].status = IRQ_DISABLED;
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+ irq_desc[i].action = NULL;
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