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dd47afc197
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c315ce403b
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/*
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* D-Link DIR-615 rev. E4 board support |
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* |
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <asm/mach-ar71xx/ar71xx.h> |
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#include "machtype.h" |
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#include "devices.h" |
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#include "dev-m25p80.h" |
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#include "dev-ap91-pci.h" |
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#include "dev-gpio-buttons.h" |
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#include "dev-leds-gpio.h" |
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#include "nvram.h" |
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#define DIR_615_E4_GPIO_LED_WPS 0 |
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#define DIR_615_E4_GPIO_LED_POWER_AMBER 1 |
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#define DIR_615_E4_GPIO_LED_POWER_GREEN 6 |
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#define DIR_615_E4_GPIO_LED_WAN_AMBER 7 |
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#define DIR_615_E4_GPIO_LED_WAN_GREEN 17 |
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#define DIR_615_E4_GPIO_LED_LAN1_GREEN 13 |
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#define DIR_615_E4_GPIO_LED_LAN2_GREEN 14 |
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#define DIR_615_E4_GPIO_LED_LAN3_GREEN 15 |
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#define DIR_615_E4_GPIO_LED_LAN4_GREEN 16 |
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#define DIR_615_E4_GPIO_BTN_RESET 8 |
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#define DIR_615_E4_GPIO_BTN_WPS 12 |
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#define DIR_615_E4_KEYS_POLL_INTERVAL 20 |
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#define DIR_615_E4_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_E4_KEYS_POLL_INTERVAL) |
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#define DIR_615_E4_NVRAM_ADDR 0x1f030000 |
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#define DIR_615_E4_NVRAM_SIZE 0x10000 |
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#ifdef CONFIG_MTD_PARTITIONS |
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static struct mtd_partition dir_615_e4_partitions[] = { |
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{ |
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.name = "u-boot", |
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.offset = 0, |
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.size = 0x030000, |
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.mask_flags = MTD_WRITEABLE, |
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}, { |
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.name = "nvram", |
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.offset = 0x030000, |
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.size = 0x010000, |
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}, { |
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.name = "kernel", |
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.offset = 0x040000, |
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.size = 0x0e0000, |
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}, { |
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.name = "rootfs", |
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.offset = 0x120000, |
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.size = 0x2c0000, |
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}, { |
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.name = "mac", |
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.offset = 0x3e0000, |
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.size = 0x010000, |
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.mask_flags = MTD_WRITEABLE, |
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}, { |
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.name = "art", |
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.offset = 0x3f0000, |
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.size = 0x010000, |
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.mask_flags = MTD_WRITEABLE, |
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}, { |
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.name = "firmware", |
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.offset = 0x040000, |
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.size = 0x3a0000, |
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} |
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}; |
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#endif /* CONFIG_MTD_PARTITIONS */ |
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static struct flash_platform_data dir_615_e4_flash_data = { |
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#ifdef CONFIG_MTD_PARTITIONS |
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.parts = dir_615_e4_partitions, |
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.nr_parts = ARRAY_SIZE(dir_615_e4_partitions), |
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#endif |
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}; |
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static struct gpio_led dir_615_e4_leds_gpio[] __initdata = { |
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{ |
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.name = "d-link:green:power", |
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.gpio = DIR_615_E4_GPIO_LED_POWER_GREEN, |
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}, { |
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.name = "d-link:amber:power", |
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.gpio = DIR_615_E4_GPIO_LED_POWER_AMBER, |
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}, { |
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.name = "d-link:green:wan", |
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.gpio = DIR_615_E4_GPIO_LED_WAN_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:amber:wan", |
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.gpio = DIR_615_E4_GPIO_LED_WAN_AMBER, |
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}, { |
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.name = "d-link:green:lan1", |
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.gpio = DIR_615_E4_GPIO_LED_LAN1_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:green:lan2", |
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.gpio = DIR_615_E4_GPIO_LED_LAN2_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:green:lan3", |
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.gpio = DIR_615_E4_GPIO_LED_LAN3_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:green:lan4", |
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.gpio = DIR_615_E4_GPIO_LED_LAN4_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:blue:wps", |
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.gpio = DIR_615_E4_GPIO_LED_WPS, |
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.active_low = 1, |
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} |
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}; |
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static struct gpio_keys_button dir_615_e4_gpio_keys[] __initdata = { |
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{ |
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.desc = "reset", |
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.type = EV_KEY, |
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.code = KEY_RESTART, |
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.debounce_interval = DIR_615_E4_KEYS_DEBOUNCE_INTERVAL, |
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.gpio = DIR_615_E4_GPIO_BTN_RESET, |
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.active_low = 1, |
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}, { |
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.desc = "wps", |
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.type = EV_KEY, |
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.code = KEY_WPS_BUTTON, |
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.debounce_interval = DIR_615_E4_KEYS_DEBOUNCE_INTERVAL, |
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.gpio = DIR_615_E4_GPIO_BTN_WPS, |
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.active_low = 1, |
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} |
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}; |
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static void __init dir_615_e4_setup(void) |
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{ |
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const char *nvram = (char *) KSEG1ADDR(DIR_615_E4_NVRAM_ADDR); |
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u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); |
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u8 mac_buff[6]; |
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u8 *mac = NULL; |
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if (nvram_parse_mac_addr(nvram, DIR_615_E4_NVRAM_SIZE, |
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"lan_mac=", mac_buff) == 0) { |
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ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac_buff, 0); |
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ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac_buff, 1); |
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mac = mac_buff; |
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} |
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ar71xx_add_device_m25p80(&dir_615_e4_flash_data); |
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ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615_e4_leds_gpio), |
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dir_615_e4_leds_gpio); |
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ar71xx_register_gpio_keys_polled(-1, DIR_615_E4_KEYS_POLL_INTERVAL, |
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ARRAY_SIZE(dir_615_e4_gpio_keys), |
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dir_615_e4_gpio_keys); |
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ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); |
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ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); |
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ar71xx_add_device_mdio(0, 0x0); |
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/* LAN ports */ |
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ar71xx_add_device_eth(1); |
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/* WAN port */ |
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ar71xx_add_device_eth(0); |
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ap91_pci_setup_wmac_led_pin(1); |
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ap91_pci_init(ee, mac); |
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} |
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MIPS_MACHINE(AR71XX_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4", |
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dir_615_e4_setup); |
@ -1,179 +0,0 @@ |
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/*
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* D-Link DIR-615 rev. E4 board support |
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* |
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <asm/mach-ath79/ath79.h> |
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#include "dev-ap9x-pci.h" |
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#include "dev-eth.h" |
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#include "dev-gpio-buttons.h" |
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#include "dev-leds-gpio.h" |
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#include "dev-m25p80.h" |
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#include "machtypes.h" |
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#include "nvram.h" |
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#define DIR_615_E4_GPIO_LED_WPS 0 |
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#define DIR_615_E4_GPIO_LED_POWER_AMBER 1 |
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#define DIR_615_E4_GPIO_LED_POWER_GREEN 6 |
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#define DIR_615_E4_GPIO_LED_WAN_AMBER 7 |
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#define DIR_615_E4_GPIO_LED_WAN_GREEN 17 |
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#define DIR_615_E4_GPIO_LED_LAN1_GREEN 13 |
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#define DIR_615_E4_GPIO_LED_LAN2_GREEN 14 |
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#define DIR_615_E4_GPIO_LED_LAN3_GREEN 15 |
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#define DIR_615_E4_GPIO_LED_LAN4_GREEN 16 |
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#define DIR_615_E4_GPIO_BTN_RESET 8 |
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#define DIR_615_E4_GPIO_BTN_WPS 12 |
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#define DIR_615_E4_KEYS_POLL_INTERVAL 20 |
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#define DIR_615_E4_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_E4_KEYS_POLL_INTERVAL) |
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#define DIR_615_E4_NVRAM_ADDR 0x1f030000 |
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#define DIR_615_E4_NVRAM_SIZE 0x10000 |
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static struct mtd_partition dir_615_e4_partitions[] = { |
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{ |
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.name = "u-boot", |
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.offset = 0, |
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.size = 0x030000, |
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.mask_flags = MTD_WRITEABLE, |
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}, { |
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.name = "nvram", |
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.offset = 0x030000, |
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.size = 0x010000, |
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}, { |
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.name = "kernel", |
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.offset = 0x040000, |
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.size = 0x0e0000, |
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}, { |
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.name = "rootfs", |
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.offset = 0x120000, |
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.size = 0x2c0000, |
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}, { |
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.name = "mac", |
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.offset = 0x3e0000, |
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.size = 0x010000, |
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.mask_flags = MTD_WRITEABLE, |
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}, { |
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.name = "art", |
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.offset = 0x3f0000, |
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.size = 0x010000, |
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.mask_flags = MTD_WRITEABLE, |
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}, { |
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.name = "firmware", |
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.offset = 0x040000, |
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.size = 0x3a0000, |
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} |
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}; |
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static struct flash_platform_data dir_615_e4_flash_data = { |
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.parts = dir_615_e4_partitions, |
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.nr_parts = ARRAY_SIZE(dir_615_e4_partitions), |
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}; |
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static struct gpio_led dir_615_e4_leds_gpio[] __initdata = { |
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{ |
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.name = "d-link:green:power", |
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.gpio = DIR_615_E4_GPIO_LED_POWER_GREEN, |
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}, { |
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.name = "d-link:amber:power", |
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.gpio = DIR_615_E4_GPIO_LED_POWER_AMBER, |
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}, { |
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.name = "d-link:green:wan", |
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.gpio = DIR_615_E4_GPIO_LED_WAN_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:amber:wan", |
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.gpio = DIR_615_E4_GPIO_LED_WAN_AMBER, |
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}, { |
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.name = "d-link:green:lan1", |
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.gpio = DIR_615_E4_GPIO_LED_LAN1_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:green:lan2", |
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.gpio = DIR_615_E4_GPIO_LED_LAN2_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:green:lan3", |
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.gpio = DIR_615_E4_GPIO_LED_LAN3_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:green:lan4", |
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.gpio = DIR_615_E4_GPIO_LED_LAN4_GREEN, |
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.active_low = 1, |
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}, { |
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.name = "d-link:blue:wps", |
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.gpio = DIR_615_E4_GPIO_LED_WPS, |
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.active_low = 1, |
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} |
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}; |
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static struct gpio_keys_button dir_615_e4_gpio_keys[] __initdata = { |
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{ |
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.desc = "reset", |
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.type = EV_KEY, |
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.code = KEY_RESTART, |
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.debounce_interval = DIR_615_E4_KEYS_DEBOUNCE_INTERVAL, |
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.gpio = DIR_615_E4_GPIO_BTN_RESET, |
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.active_low = 1, |
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}, { |
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.desc = "wps", |
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.type = EV_KEY, |
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.code = KEY_WPS_BUTTON, |
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.debounce_interval = DIR_615_E4_KEYS_DEBOUNCE_INTERVAL, |
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.gpio = DIR_615_E4_GPIO_BTN_WPS, |
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.active_low = 1, |
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} |
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}; |
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static void __init dir_615_e4_setup(void) |
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{ |
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const char *nvram = (char *) KSEG1ADDR(DIR_615_E4_NVRAM_ADDR); |
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u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); |
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u8 mac_buff[6]; |
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u8 *mac = NULL; |
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if (ath79_nvram_parse_mac_addr(nvram, DIR_615_E4_NVRAM_SIZE, |
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"lan_mac=", mac_buff) == 0) { |
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ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0); |
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ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1); |
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mac = mac_buff; |
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} |
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ath79_register_m25p80(&dir_615_e4_flash_data); |
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ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615_e4_leds_gpio), |
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dir_615_e4_leds_gpio); |
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ath79_register_gpio_keys_polled(-1, DIR_615_E4_KEYS_POLL_INTERVAL, |
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ARRAY_SIZE(dir_615_e4_gpio_keys), |
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dir_615_e4_gpio_keys); |
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ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); |
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ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); |
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ath79_register_mdio(0, 0x0); |
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/* LAN ports */ |
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ath79_register_eth(1); |
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/* WAN port */ |
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ath79_register_eth(0); |
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ap9x_pci_setup_wmac_led_pin(0, 1); |
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ap91_pci_init(ee, mac); |
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} |
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MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4", |
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dir_615_e4_setup); |
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