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@ -90,6 +90,8 @@ static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info) |
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break; |
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} |
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info |= ED_SKIP; |
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ed->dummy = td; |
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ed->state = ED_NEW; |
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ed->type = type; |
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@ -112,10 +114,8 @@ err: |
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static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep, |
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struct usb_device *udev, unsigned int pipe, int interval) |
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{ |
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struct ed *ed; |
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unsigned long flags; |
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struct ed *ed; |
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spin_lock_irqsave(&ahcd->lock, flags); |
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ed = ep->hcpriv; |
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if (!ed) { |
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u32 info; |
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@ -133,11 +133,33 @@ static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep, |
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if (ed) |
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ep->hcpriv = ed; |
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} |
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spin_unlock_irqrestore(&ahcd->lock, flags); |
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return ed; |
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} |
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static void ed_next_urb(struct admhcd *ahcd, struct ed *ed) |
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{ |
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struct urb_priv *up; |
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u32 carry; |
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up = list_entry(ed->urb_pending.next, struct urb_priv, pending); |
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list_del(&up->pending); |
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ed->urb_active = up; |
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ed->state = ED_OPER; |
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#ifdef ADMHC_VERBOSE_DEBUG |
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urb_print(ahcd, up->urb, "NEXT", 0); |
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admhc_dump_ed(ahcd, " ", ed, 0); |
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#endif |
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up->td[up->td_cnt-1]->hwNextTD = cpu_to_hc32(ahcd, ed->dummy->td_dma); |
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carry = hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_C; |
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ed->hwHeadP = cpu_to_hc32(ahcd, up->td[0]->td_dma | carry); |
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ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP); |
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} |
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/* link an ed into the HC chain */ |
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static int ed_schedule(struct admhcd *ahcd, struct ed *ed) |
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{ |
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@ -146,37 +168,43 @@ static int ed_schedule(struct admhcd *ahcd, struct ed *ed) |
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if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING) |
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return -EAGAIN; |
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if (ed->state != ED_NEW) |
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return 0; |
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if (ed->state == ED_NEW) { |
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ed->state = ED_IDLE; |
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admhc_dump_ed(ahcd, "ED-SCHED", ed, 0); |
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ed->state = ED_IDLE; |
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old_tail = ahcd->ed_tails[ed->type]; |
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ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP); |
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ed->ed_next = old_tail->ed_next; |
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if (ed->ed_next) { |
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ed->ed_next->ed_prev = ed; |
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ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma); |
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} |
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ed->ed_prev = old_tail; |
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old_tail = ahcd->ed_tails[ed->type]; |
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old_tail->ed_next = ed; |
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old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma); |
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ed->ed_next = old_tail->ed_next; |
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if (ed->ed_next) { |
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ed->ed_next->ed_prev = ed; |
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ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma); |
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ahcd->ed_tails[ed->type] = ed; |
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ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP); |
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} |
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ed->ed_prev = old_tail; |
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old_tail->ed_next = ed; |
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old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma); |
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ahcd->ed_tails[ed->type] = ed; |
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#ifdef ADMHC_VERBOSE_DEBUG |
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admhc_dump_ed(ahcd, "ED-SCHED", ed, 0); |
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#endif |
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admhc_intr_enable(ahcd, ADMHC_INTR_SOFI); |
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if (!ed->urb_active) { |
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ed_next_urb(ahcd, ed); |
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admhc_dma_enable(ahcd); |
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} |
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return 0; |
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} |
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static void ed_deschedule(struct admhcd *ahcd, struct ed *ed) |
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{ |
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#ifdef ADMHC_VERBOSE_DEBUG |
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admhc_dump_ed(ahcd, "ED-DESCHED", ed, 0); |
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#endif |
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/* remove this ED from the HC list */ |
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ed->ed_prev->hwNextED = ed->hwNextED; |
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@ -197,16 +225,14 @@ static void ed_deschedule(struct admhcd *ahcd, struct ed *ed) |
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static void ed_start_deschedule(struct admhcd *ahcd, struct ed *ed) |
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{ |
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#ifdef ADMHC_VERBOSE_DEBUG |
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admhc_dump_ed(ahcd, "ED-UNLINK", ed, 0); |
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#endif |
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ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP); |
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ed->state = ED_UNLINK; |
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/* add this ED into the remove list */ |
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ed->ed_rm_next = ahcd->ed_rm_list; |
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ahcd->ed_rm_list = ed; |
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/* SOF interrupt might get delayed; record the frame counter value that
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* indicates when the HC isn't looking at it, so concurrent unlinks |
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* behave. frame_no wraps every 2^16 msec, and changes right before |
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@ -214,7 +240,6 @@ static void ed_start_deschedule(struct admhcd *ahcd, struct ed *ed) |
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*/ |
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ed->tick = admhc_frame_no(ahcd) + 1; |
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/* enable SOF interrupt */ |
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admhc_intr_enable(ahcd, ADMHC_INTR_SOFI); |
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} |
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@ -229,9 +254,9 @@ static void td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len, |
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u32 cbl = 0; |
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if (up->td_idx >= up->td_cnt) { |
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admhc_dbg(ahcd, "td_fill error, idx=%d, cnt=%d\n", up->td_idx, |
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admhc_err(ahcd, "td_fill error, idx=%d, cnt=%d\n", up->td_idx, |
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up->td_cnt); |
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return; |
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BUG(); |
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} |
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td = up->td[up->td_idx]; |
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@ -239,9 +264,7 @@ static void td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len, |
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if (!len) |
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data = 0; |
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#if 1 |
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if (up->td_idx == up->td_cnt-1) |
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#endif |
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cbl |= TD_IE; |
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if (data) |
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@ -446,7 +469,10 @@ static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td) |
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* might not be reported as errors. |
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*/ |
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} else { |
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#ifdef ADMHC_VERBOSE_DEBUG |
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admhc_dump_td(ahcd, "td_done", td); |
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#endif |
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/* count all non-empty packets except control SETUP packet */ |
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if ((type != PIPE_CONTROL || td->index != 0) && dbp != 0) { |
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@ -459,122 +485,7 @@ static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td) |
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/*-------------------------------------------------------------------------*/ |
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static inline struct td * |
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ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev) |
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{ |
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#if 0 |
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struct urb *urb = td->urb; |
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struct ed *ed = td->ed; |
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struct list_head *tmp = td->td_list.next; |
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__hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ahcd, ED_C); |
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admhc_dump_ed(ahcd, "ed halted", td->ed, 1); |
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/* clear ed halt; this is the td that caused it, but keep it inactive
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* until its urb->complete() has a chance to clean up. |
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*/ |
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ed->hwINFO |= cpu_to_hc32 (ahcd, ED_SKIP); |
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|
wmb (); |
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ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H); |
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/* put any later tds from this urb onto the donelist, after 'td',
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* order won't matter here: no errors, and nothing was transferred. |
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|
* also patch the ed so it looks as if those tds completed normally. |
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|
*/ |
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|
while (tmp != &ed->td_list) { |
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|
struct td *next; |
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|
__hc32 info; |
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next = list_entry(tmp, struct td, td_list); |
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tmp = next->td_list.next; |
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|
if (next->urb != urb) |
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|
break; |
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|
|
/* NOTE: if multi-td control DATA segments get supported,
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|
* this urb had one of them, this td wasn't the last td |
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|
* in that segment (TD_R clear), this ed halted because |
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|
* of a short read, _and_ URB_SHORT_NOT_OK is clear ... |
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|
* then we need to leave the control STATUS packet queued |
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|
* and clear ED_SKIP. |
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|
*/ |
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|
|
info = next->hwINFO; |
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|
#if 0 /* FIXME */
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|
info |= cpu_to_hc32 (ahcd, TD_DONE); |
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|
info &= ~cpu_to_hc32 (ahcd, TD_CC); |
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|
#endif |
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|
next->hwINFO = info; |
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|
next->next_dl_td = rev; |
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|
rev = next; |
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|
ed->hwHeadP = next->hwNextTD | toggle; |
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|
} |
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|
|
/* help for troubleshooting: report anything that
|
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|
|
* looks odd ... that doesn't include protocol stalls |
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|
* (or maybe some other things) |
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|
*/ |
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|
switch (cc) { |
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|
case TD_CC_DATAUNDERRUN: |
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|
if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0) |
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|
break; |
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|
|
/* fallthrough */ |
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|
|
case TD_CC_STALL: |
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|
|
if (usb_pipecontrol (urb->pipe)) |
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|
break; |
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|
|
/* fallthrough */ |
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|
default: |
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|
|
admhc_dbg (ahcd, |
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|
"urb %p path %s ep%d%s %08x cc %d --> status %d\n", |
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|
|
urb, urb->dev->devpath, |
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|
|
usb_pipeendpoint (urb->pipe), |
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|
|
usb_pipein (urb->pipe) ? "in" : "out", |
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|
|
hc32_to_cpu(ahcd, td->hwINFO), |
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|
cc, cc_to_error [cc]); |
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|
} |
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|
return rev; |
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|
#else |
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|
return NULL; |
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|
#endif |
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|
|
} |
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|
|
/*-------------------------------------------------------------------------*/ |
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static int ed_next_urb(struct admhcd *ahcd, struct ed *ed) |
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|
|
{ |
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|
struct urb_priv *up; |
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|
u32 carry; |
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if (ed->state != ED_IDLE) |
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|
return 1; |
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if (ed->urb_active) |
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return 1; |
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|
if (list_empty(&ed->urb_pending)) |
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|
return 0; |
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|
|
up = list_entry(ed->urb_pending.next, struct urb_priv, pending); |
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|
|
list_del(&up->pending); |
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|
|
ed->urb_active = up; |
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|
|
ed->state = ED_OPER; |
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|
|
#ifdef ADMHC_VERBOSE_DEBUG |
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|
|
urb_print(ahcd, up->urb, "NEXT", 0); |
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|
|
admhc_dump_ed(ahcd, " ", ed, 0); |
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|
#endif |
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|
|
up->td[up->td_cnt-1]->hwNextTD = cpu_to_hc32(ahcd, ed->dummy->td_dma); |
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|
|
carry = hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_C; |
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|
|
ed->hwHeadP = cpu_to_hc32(ahcd, up->td[0]->td_dma | carry); |
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|
|
ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP); |
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|
return 1; |
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|
|
} |
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|
|
static void ed_update(struct admhcd *ahcd, struct ed *ed, int partial) |
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|
|
static void ed_update(struct admhcd *ahcd, struct ed *ed, int force) |
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|
|
{ |
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|
|
struct urb_priv *up; |
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|
|
struct urb *urb; |
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|
|
@ -588,8 +499,8 @@ static void ed_update(struct admhcd *ahcd, struct ed *ed, int partial) |
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|
|
#ifdef ADMHC_VERBOSE_DEBUG |
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|
|
urb_print(ahcd, urb, "UPDATE", 0); |
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|
|
#endif |
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|
|
admhc_dump_ed(ahcd, "ED-UPDATE", ed, 1); |
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|
|
#endif |
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|
|
cc = TD_CC_NOERROR; |
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|
|
for (; up->td_idx < up->td_cnt; up->td_idx++) { |
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|
|
@ -611,7 +522,7 @@ static void ed_update(struct admhcd *ahcd, struct ed *ed, int partial) |
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|
|
} |
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|
|
} |
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|
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|
|
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|
|
if ((up->td_idx != up->td_cnt) && (!partial)) |
|
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|
|
if ((up->td_idx != up->td_cnt) && (!force)) |
|
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|
|
/* the URB is not completed yet */ |
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|
|
return; |
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|
|
|
|
|
|
|
@ -637,68 +548,65 @@ static void ed_update(struct admhcd *ahcd, struct ed *ed, int partial) |
|
|
|
|
static void admhc_td_complete(struct admhcd *ahcd) |
|
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|
|
{ |
|
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|
|
struct ed *ed; |
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|
|
int more = 0; |
|
|
|
|
|
|
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|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) { |
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|
|
if (ed->state != ED_OPER) |
|
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|
|
continue; |
|
|
|
|
|
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwINFO) & ED_SKIP) |
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) { |
|
|
|
|
admhc_dump_ed(ahcd, "ed halted", ed, 1); |
|
|
|
|
ed_update(ahcd, ed, 1); |
|
|
|
|
ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H); |
|
|
|
|
} else |
|
|
|
|
ed_update(ahcd, ed, 0); |
|
|
|
|
|
|
|
|
|
if (ed->urb_active) { |
|
|
|
|
more = 1; |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) { |
|
|
|
|
/* TODO */ |
|
|
|
|
if (!(list_empty(&ed->urb_pending))) { |
|
|
|
|
more = 1; |
|
|
|
|
ed_next_urb(ahcd, ed); |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
ed_update(ahcd, ed, 0); |
|
|
|
|
ed_start_deschedule(ahcd, ed); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (!more) |
|
|
|
|
admhc_dma_disable(ahcd); |
|
|
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */ |
|
|
|
|
static void admhc_finish_unlinks(struct admhcd *ahcd, u16 tick) |
|
|
|
|
{ |
|
|
|
|
struct ed *ed; |
|
|
|
|
int more = 0; |
|
|
|
|
|
|
|
|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) { |
|
|
|
|
if (ed->state != ED_UNLINK) |
|
|
|
|
continue; |
|
|
|
|
|
|
|
|
|
if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) |
|
|
|
|
if (tick_before(tick, ed->tick)) |
|
|
|
|
if (tick_before(tick, ed->tick)) { |
|
|
|
|
more = 1; |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* process partial status */ |
|
|
|
|
ed_update(ahcd, ed, 1); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static void admhc_sof_refill(struct admhcd *ahcd) |
|
|
|
|
{ |
|
|
|
|
struct ed *ed; |
|
|
|
|
int disable_dma = 1; |
|
|
|
|
|
|
|
|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) { |
|
|
|
|
|
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) { |
|
|
|
|
if (ed->urb_active) |
|
|
|
|
ed_update(ahcd, ed, 1); |
|
|
|
|
ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (ed_next_urb(ahcd, ed)) { |
|
|
|
|
disable_dma = 0; |
|
|
|
|
} else { |
|
|
|
|
struct ed *tmp; |
|
|
|
|
tmp = ed->ed_prev; |
|
|
|
|
if (list_empty(&ed->urb_pending)) |
|
|
|
|
ed_deschedule(ahcd, ed); |
|
|
|
|
ed = tmp; |
|
|
|
|
} |
|
|
|
|
else |
|
|
|
|
ed_schedule(ahcd, ed); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (disable_dma) { |
|
|
|
|
admhc_intr_disable(ahcd, ADMHC_INTR_SOFI); |
|
|
|
|
admhc_dma_disable(ahcd); |
|
|
|
|
} else { |
|
|
|
|
admhc_intr_enable(ahcd, ADMHC_INTR_SOFI); |
|
|
|
|
admhc_dma_enable(ahcd); |
|
|
|
|
} |
|
|
|
|
if (!more) |
|
|
|
|
if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) |
|
|
|
|
admhc_intr_disable(ahcd, ADMHC_INTR_SOFI); |
|
|
|
|
} |
|
|
|
|