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Register the second uart on tnetd7300 and fix the watchdog register for 7200/7300, thanks to DerAgo (#2149)

Browse Source 
SVN-Revision: 8280
master
Florian Fainelli 18 years ago
parent 51dfaf45b4
commit ba3a37436e
3 changed files with 90 additions and 56 deletions
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  1. 89
      target/linux/ar7-2.6/files/arch/mips/ar7/platform.c
  2. 38
      target/linux/ar7-2.6/files/drivers/char/watchdog/ar7_wdt.c
  3. 19
      target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h

89
target/linux/ar7-2.6/files/arch/mips/ar7/platform.c
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@ -252,30 +252,40 @@ static struct platform_device vlynq_high = {
* as xscale and, obviously, don't work...
*/
#if !defined(CONFIG_SERIAL_8250)
static struct plat_serial8250_port uart0_data =
{
.mapbase = AR7_REGS_UART0,
.irq = AR7_IRQ_UART0,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
};
static struct plat_serial8250_port uart1_data =
{
.mapbase = UR8_REGS_UART1,
.irq = AR7_IRQ_UART1,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
};
static struct plat_serial8250_port uart_data[] = {
{
.mapbase = AR7_REGS_UART0,
.irq = AR7_IRQ_UART0,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
},
{
.mapbase = AR7_REGS_UART1,
.irq = AR7_IRQ_UART1,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
},
{
.flags = 0,
},
uart0_data,
uart1_data,
{ .flags = 0 }
};
static struct plat_serial8250_port uart_data_single[] = {
uart0_data,
{ .flags = 0 }
};
static struct platform_device uart = {
.id = 0,
.name = "serial8250",
.dev.platform_data = uart_data,
.dev.platform_data = uart_data_single
};
#endif
@ -317,7 +327,8 @@ static int __init ar7_register_devices(void)
{
int res;
#if defined(CONFIG_SERIAL_8250)
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port[2];
memset(uart_port, 0, sizeof(struct uart_port) * 2);
@ -334,24 +345,38 @@ static int __init ar7_register_devices(void)
if (res)
return res;
uart_port[1].type = PORT_AR7;
uart_port[1].line = 1;
uart_port[1].irq = AR7_IRQ_UART1;
uart_port[1].uartclk = ar7_bus_freq() / 2;
uart_port[1].iotype = UPIO_MEM;
uart_port[1].mapbase = AR7_REGS_UART1;
uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
uart_port[1].regshift = 2;
res = early_serial_setup(&uart_port[1]);
if (res)
return res;
#else
// Only TNETD73xx have a second serial port
if (ar7_has_second_uart()) {
uart_port[1].type = PORT_AR7;
uart_port[1].line = 1;
uart_port[1].irq = AR7_IRQ_UART1;
uart_port[1].uartclk = ar7_bus_freq() / 2;
uart_port[1].iotype = UPIO_MEM;
uart_port[1].mapbase = UR8_REGS_UART1;
uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
uart_port[1].regshift = 2;
res = early_serial_setup(&uart_port[1]);
if (res)
return res;
}
#else // !CONFIG_SERIAL_8250
uart_data[0].uartclk = ar7_bus_freq() / 2;
uart_data[1].uartclk = uart_data[0].uartclk;
// Only TNETD73xx have a second serial port
if (ar7_has_second_uart()) {
uart.dev.platform_data = uart_data;
}
res = platform_device_register(&uart);
if (res)
return res;
#endif
#endif // CONFIG_SERIAL_8250
res = platform_device_register(&physmap_flash);
if (res)
return res;

38
target/linux/ar7-2.6/files/drivers/char/watchdog/ar7_wdt.c
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@ -73,10 +73,27 @@ static unsigned expect_close;
/* XXX currently fixed, allows max margin ~68.72 secs */
#define prescale_value 0xFFFF
// Offset of the WDT registers
static unsigned long ar7_regs_wdt;
// Pointer to the remapped WDT IO space
static ar7_wdt_t *ar7_wdt;
static void ar7_wdt_get_regs(void)
{
u16 chip_id = ar7_chip_id();
switch (chip_id)
{
case AR7_CHIP_7100:
case AR7_CHIP_7200:
ar7_regs_wdt = AR7_REGS_WDT;
break;
default:
ar7_regs_wdt = UR8_REGS_WDT;
break;
}
}
static void ar7_wdt_kick(u32 value)
{
volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
ar7_wdt->kick_lock = 0x5555;
if ((ar7_wdt->kick_lock & 3) == 1) {
ar7_wdt->kick_lock = 0xAAAA;
@ -90,8 +107,6 @@ static void ar7_wdt_kick(u32 value)
static void ar7_wdt_prescale(u32 value)
{
volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
ar7_wdt->prescale_lock = 0x5A5A;
if ((ar7_wdt->prescale_lock & 3) == 1) {
ar7_wdt->prescale_lock = 0xA5A5;
@ -105,8 +120,6 @@ static void ar7_wdt_prescale(u32 value)
static void ar7_wdt_change(u32 value)
{
volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
ar7_wdt->change_lock = 0x6666;
if ((ar7_wdt->change_lock & 3) == 1) {
ar7_wdt->change_lock = 0xBBBB;
@ -120,8 +133,6 @@ static void ar7_wdt_change(u32 value)
static void ar7_wdt_disable(u32 value)
{
volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
ar7_wdt->disable_lock = 0x7777;
if ((ar7_wdt->disable_lock & 3) == 1) {
ar7_wdt->disable_lock = 0xCCCC;
@ -285,12 +296,16 @@ static struct miscdevice ar7_wdt_miscdev = {
static int __init ar7_wdt_init(void)
{
int rc;
ar7_wdt_get_regs();
if (!request_mem_region(AR7_REGS_WDT, sizeof(ar7_wdt_t), LONGNAME)) {
if (!request_mem_region(ar7_regs_wdt, sizeof(ar7_wdt_t), LONGNAME)) {
printk(KERN_WARNING DRVNAME ": watchdog I/O region busy\n");
return -EBUSY;
}
ar7_wdt = (ar7_wdt_t *)ioremap(ar7_regs_wdt, sizeof(ar7_wdt_t));
ar7_wdt_disable_wdt();
ar7_wdt_prescale(prescale_value);
ar7_wdt_update_margin(margin);
@ -313,7 +328,7 @@ static int __init ar7_wdt_init(void)
out_register:
misc_deregister(&ar7_wdt_miscdev);
out_alloc:
release_mem_region(AR7_REGS_WDT, sizeof(ar7_wdt_t));
release_mem_region(ar7_regs_wdt, sizeof(ar7_wdt_t));
out:
return rc;
}
@ -322,7 +337,8 @@ static void __exit ar7_wdt_cleanup(void)
{
unregister_reboot_notifier(&ar7_wdt_notifier);
misc_deregister(&ar7_wdt_miscdev);
release_mem_region(AR7_REGS_WDT, sizeof(ar7_wdt_t));
iounmap(ar7_wdt);
release_mem_region(ar7_regs_wdt, sizeof(ar7_wdt_t));
}
module_init(ar7_wdt_init);

19
target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
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@ -28,27 +28,21 @@
#define AR7_REGS_BASE 0x08610000
#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
#define AR7_REGS_EMIF (AR7_REGS_BASE + 0x0800)
#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
#define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock)
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
#define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
#define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000)
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
#define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400)
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
#define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700)
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00)
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00)
#define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000)
#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
#define AR7_RESET_PEREPHERIAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
@ -64,8 +58,6 @@
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xC
#define AR7_GPIO_BIT_STATUS_LED 8
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
@ -131,6 +123,7 @@ static inline int ar7_has_high_cpmac(void)
}
}
#define ar7_has_high_vlynq ar7_has_high_cpmac
#define ar7_has_second_uart ar7_has_high_cpmac
static inline void ar7_device_enable(u32 bit)
{

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