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@ -5,7 +5,7 @@ |
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#define RT305X_ESW_REG_FCT0 0x08 |
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#define RT305X_ESW_REG_PFC1 0x14 |
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#define RT305X_ESW_REG_PVIDC(_n) (0x48 + 4 * (_n)) |
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#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n)) |
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#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n)) |
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#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n)) |
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#define RT305X_ESW_REG_FPA 0x84 |
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@ -172,7 +172,7 @@ rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid) |
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s = RT305X_ESW_PVIDC_PVID_S * (port % 2); |
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rt305x_esw_rmw(esw, |
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RT305X_ESW_REG_PVIDC(port / 2), |
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RT305X_ESW_PVIDC_PVID_S << s, |
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RT305X_ESW_PVIDC_PVID_M << s, |
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(pvid & RT305X_ESW_PVIDC_PVID_M) << s); |
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} |
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