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@ -38,6 +38,7 @@ |
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#include <linux/mutex.h> |
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#include <linux/slab.h> |
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#include <asm/mach-ar71xx/ar933x_uart.h> |
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#include <asm/mach-ar71xx/ar933x_uart_platform.h> |
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#include <asm/io.h> |
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@ -51,271 +52,6 @@ |
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#define AR933X_UART_REGS_SIZE 20 |
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#define AR933X_UART_FIFO_SIZE 16 |
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/*
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* Uart block |
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*/ |
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#define UARTDATA_UARTTXCSR_MSB 9 |
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#define UARTDATA_UARTTXCSR_LSB 9 |
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#define UARTDATA_UARTTXCSR_MASK 0x00000200 |
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#define UARTDATA_UARTTXCSR_GET(x) (((x) & UARTDATA_UARTTXCSR_MASK) >> UARTDATA_UARTTXCSR_LSB) |
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#define UARTDATA_UARTTXCSR_SET(x) (((0 | (x)) << UARTDATA_UARTTXCSR_LSB) & UARTDATA_UARTTXCSR_MASK) |
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#define UARTDATA_UARTTXCSR_RESET 0 |
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#define UARTDATA_UARTRXCSR_MSB 8 |
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#define UARTDATA_UARTRXCSR_LSB 8 |
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#define UARTDATA_UARTRXCSR_MASK 0x00000100 |
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#define UARTDATA_UARTRXCSR_GET(x) (((x) & UARTDATA_UARTRXCSR_MASK) >> UARTDATA_UARTRXCSR_LSB) |
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#define UARTDATA_UARTRXCSR_SET(x) (((0 | (x)) << UARTDATA_UARTRXCSR_LSB) & UARTDATA_UARTRXCSR_MASK) |
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#define UARTDATA_UARTRXCSR_RESET 0 |
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#define UARTDATA_UARTTXRXDATA_MSB 7 |
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#define UARTDATA_UARTTXRXDATA_LSB 0 |
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#define UARTDATA_UARTTXRXDATA_MASK 0x000000ff |
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#define UARTDATA_UARTTXRXDATA_GET(x) (((x) & UARTDATA_UARTTXRXDATA_MASK) >> UARTDATA_UARTTXRXDATA_LSB) |
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#define UARTDATA_UARTTXRXDATA_SET(x) (((0 | (x)) << UARTDATA_UARTTXRXDATA_LSB) & UARTDATA_UARTTXRXDATA_MASK) |
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#define UARTDATA_UARTTXRXDATA_RESET 0 |
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#define UARTDATA_ADDRESS 0x0000 |
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#define UARTDATA_HW_MASK 0x000003ff |
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#define UARTDATA_SW_MASK 0x000003ff |
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#define UARTDATA_RSTMASK 0x000003ff |
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#define UARTDATA_RESET 0x00000000 |
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// 0x0004 (UARTCS)
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#define UARTCS_UARTRXBUSY_MSB 15 |
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#define UARTCS_UARTRXBUSY_LSB 15 |
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#define UARTCS_UARTRXBUSY_MASK 0x00008000 |
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#define UARTCS_UARTRXBUSY_GET(x) (((x) & UARTCS_UARTRXBUSY_MASK) >> UARTCS_UARTRXBUSY_LSB) |
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#define UARTCS_UARTRXBUSY_SET(x) (((0 | (x)) << UARTCS_UARTRXBUSY_LSB) & UARTCS_UARTRXBUSY_MASK) |
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#define UARTCS_UARTRXBUSY_RESET 0 |
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#define UARTCS_UARTTXBUSY_MSB 14 |
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#define UARTCS_UARTTXBUSY_LSB 14 |
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#define UARTCS_UARTTXBUSY_MASK 0x00004000 |
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#define UARTCS_UARTTXBUSY_GET(x) (((x) & UARTCS_UARTTXBUSY_MASK) >> UARTCS_UARTTXBUSY_LSB) |
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#define UARTCS_UARTTXBUSY_SET(x) (((0 | (x)) << UARTCS_UARTTXBUSY_LSB) & UARTCS_UARTTXBUSY_MASK) |
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#define UARTCS_UARTTXBUSY_RESET 0 |
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#define UARTCS_UARTHOSTINTEN_MSB 13 |
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#define UARTCS_UARTHOSTINTEN_LSB 13 |
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#define UARTCS_UARTHOSTINTEN_MASK 0x00002000 |
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#define UARTCS_UARTHOSTINTEN_GET(x) (((x) & UARTCS_UARTHOSTINTEN_MASK) >> UARTCS_UARTHOSTINTEN_LSB) |
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#define UARTCS_UARTHOSTINTEN_SET(x) (((0 | (x)) << UARTCS_UARTHOSTINTEN_LSB) & UARTCS_UARTHOSTINTEN_MASK) |
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#define UARTCS_UARTHOSTINTEN_RESET 0 |
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#define UARTCS_UARTHOSTINT_MSB 12 |
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#define UARTCS_UARTHOSTINT_LSB 12 |
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#define UARTCS_UARTHOSTINT_MASK 0x00001000 |
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#define UARTCS_UARTHOSTINT_GET(x) (((x) & UARTCS_UARTHOSTINT_MASK) >> UARTCS_UARTHOSTINT_LSB) |
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#define UARTCS_UARTHOSTINT_SET(x) (((0 | (x)) << UARTCS_UARTHOSTINT_LSB) & UARTCS_UARTHOSTINT_MASK) |
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#define UARTCS_UARTHOSTINT_RESET 0 |
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#define UARTCS_UARTTXBREAK_MSB 11 |
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#define UARTCS_UARTTXBREAK_LSB 11 |
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#define UARTCS_UARTTXBREAK_MASK 0x00000800 |
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#define UARTCS_UARTTXBREAK_GET(x) (((x) & UARTCS_UARTTXBREAK_MASK) >> UARTCS_UARTTXBREAK_LSB) |
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#define UARTCS_UARTTXBREAK_SET(x) (((0 | (x)) << UARTCS_UARTTXBREAK_LSB) & UARTCS_UARTTXBREAK_MASK) |
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#define UARTCS_UARTTXBREAK_RESET 0 |
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#define UARTCS_UARTRXBREAK_MSB 10 |
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#define UARTCS_UARTRXBREAK_LSB 10 |
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#define UARTCS_UARTRXBREAK_MASK 0x00000400 |
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#define UARTCS_UARTRXBREAK_GET(x) (((x) & UARTCS_UARTRXBREAK_MASK) >> UARTCS_UARTRXBREAK_LSB) |
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#define UARTCS_UARTRXBREAK_SET(x) (((0 | (x)) << UARTCS_UARTRXBREAK_LSB) & UARTCS_UARTRXBREAK_MASK) |
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#define UARTCS_UARTRXBREAK_RESET 0 |
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#define UARTCS_UARTSERIATXREADY_MSB 9 |
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#define UARTCS_UARTSERIATXREADY_LSB 9 |
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#define UARTCS_UARTSERIATXREADY_MASK 0x00000200 |
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#define UARTCS_UARTSERIATXREADY_GET(x) (((x) & UARTCS_UARTSERIATXREADY_MASK) >> UARTCS_UARTSERIATXREADY_LSB) |
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#define UARTCS_UARTSERIATXREADY_SET(x) (((0 | (x)) << UARTCS_UARTSERIATXREADY_LSB) & UARTCS_UARTSERIATXREADY_MASK) |
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#define UARTCS_UARTSERIATXREADY_RESET 0 |
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#define UARTCS_UARTTXREADYORIDE_MSB 8 |
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#define UARTCS_UARTTXREADYORIDE_LSB 8 |
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#define UARTCS_UARTTXREADYORIDE_MASK 0x00000100 |
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#define UARTCS_UARTTXREADYORIDE_GET(x) (((x) & UARTCS_UARTTXREADYORIDE_MASK) >> UARTCS_UARTTXREADYORIDE_LSB) |
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#define UARTCS_UARTTXREADYORIDE_SET(x) (((0 | (x)) << UARTCS_UARTTXREADYORIDE_LSB) & UARTCS_UARTTXREADYORIDE_MASK) |
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#define UARTCS_UARTTXREADYORIDE_RESET 0 |
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#define UARTCS_UARTRXREADYORIDE_MSB 7 |
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#define UARTCS_UARTRXREADYORIDE_LSB 7 |
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#define UARTCS_UARTRXREADYORIDE_MASK 0x00000080 |
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#define UARTCS_UARTRXREADYORIDE_GET(x) (((x) & UARTCS_UARTRXREADYORIDE_MASK) >> UARTCS_UARTRXREADYORIDE_LSB) |
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#define UARTCS_UARTRXREADYORIDE_SET(x) (((0 | (x)) << UARTCS_UARTRXREADYORIDE_LSB) & UARTCS_UARTRXREADYORIDE_MASK) |
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#define UARTCS_UARTRXREADYORIDE_RESET 0 |
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#define UARTCS_UARTDMAEN_MSB 6 |
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#define UARTCS_UARTDMAEN_LSB 6 |
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#define UARTCS_UARTDMAEN_MASK 0x00000040 |
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#define UARTCS_UARTDMAEN_GET(x) (((x) & UARTCS_UARTDMAEN_MASK) >> UARTCS_UARTDMAEN_LSB) |
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#define UARTCS_UARTDMAEN_SET(x) (((0 | (x)) << UARTCS_UARTDMAEN_LSB) & UARTCS_UARTDMAEN_MASK) |
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#define UARTCS_UARTDMAEN_RESET 0 |
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#define UARTCS_UARTFLOWCONTROLMODE_MSB 5 |
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#define UARTCS_UARTFLOWCONTROLMODE_LSB 4 |
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#define UARTCS_UARTFLOWCONTROLMODE_MASK 0x00000030 |
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#define UARTCS_UARTFLOWCONTROLMODE_GET(x) (((x) & UARTCS_UARTFLOWCONTROLMODE_MASK) >> UARTCS_UARTFLOWCONTROLMODE_LSB) |
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#define UARTCS_UARTFLOWCONTROLMODE_SET(x) (((0 | (x)) << UARTCS_UARTFLOWCONTROLMODE_LSB) & UARTCS_UARTFLOWCONTROLMODE_MASK) |
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#define UARTCS_UARTFLOWCONTROLMODE_RESET 0 |
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#define UARTCS_UARTINTERFACEMODE_MSB 3 |
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#define UARTCS_UARTINTERFACEMODE_LSB 2 |
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#define UARTCS_UARTINTERFACEMODE_MASK 0x0000000c |
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#define UARTCS_UARTINTERFACEMODE_GET(x) (((x) & UARTCS_UARTINTERFACEMODE_MASK) >> UARTCS_UARTINTERFACEMODE_LSB) |
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#define UARTCS_UARTINTERFACEMODE_SET(x) (((0 | (x)) << UARTCS_UARTINTERFACEMODE_LSB) & UARTCS_UARTINTERFACEMODE_MASK) |
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#define UARTCS_UARTINTERFACEMODE_RESET 0 |
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#define UARTCS_UARTPARITYMODE_MSB 1 |
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#define UARTCS_UARTPARITYMODE_LSB 0 |
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#define UARTCS_UARTPARITYMODE_MASK 0x00000003 |
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#define UARTCS_UARTPARITYMODE_GET(x) (((x) & UARTCS_UARTPARITYMODE_MASK) >> UARTCS_UARTPARITYMODE_LSB) |
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#define UARTCS_UARTPARITYMODE_SET(x) (((0 | (x)) << UARTCS_UARTPARITYMODE_LSB) & UARTCS_UARTPARITYMODE_MASK) |
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#define UARTCS_UARTPARITYMODE_RESET 0 |
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#define UARTCS_ADDRESS 0x0004 |
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#define UARTCS_HW_MASK 0x0000ffff |
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#define UARTCS_SW_MASK 0x0000ffff |
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#define UARTCS_RSTMASK 0x000029ff |
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#define UARTCS_RESET 0x00000000 |
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// 0x0008 (UARTCLOCK)
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#define UARTCLOCK_UARTCLOCKSCALE_MSB 23 |
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#define UARTCLOCK_UARTCLOCKSCALE_LSB 16 |
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#define UARTCLOCK_UARTCLOCKSCALE_MASK 0x00ff0000 |
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#define UARTCLOCK_UARTCLOCKSCALE_GET(x) (((x) & UARTCLOCK_UARTCLOCKSCALE_MASK) >> UARTCLOCK_UARTCLOCKSCALE_LSB) |
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#define UARTCLOCK_UARTCLOCKSCALE_SET(x) (((0 | (x)) << UARTCLOCK_UARTCLOCKSCALE_LSB) & UARTCLOCK_UARTCLOCKSCALE_MASK) |
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#define UARTCLOCK_UARTCLOCKSCALE_RESET 0 |
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#define UARTCLOCK_UARTCLOCKSTEP_MSB 15 |
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#define UARTCLOCK_UARTCLOCKSTEP_LSB 0 |
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#define UARTCLOCK_UARTCLOCKSTEP_MASK 0x0000ffff |
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#define UARTCLOCK_UARTCLOCKSTEP_GET(x) (((x) & UARTCLOCK_UARTCLOCKSTEP_MASK) >> UARTCLOCK_UARTCLOCKSTEP_LSB) |
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#define UARTCLOCK_UARTCLOCKSTEP_SET(x) (((0 | (x)) << UARTCLOCK_UARTCLOCKSTEP_LSB) & UARTCLOCK_UARTCLOCKSTEP_MASK) |
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#define UARTCLOCK_UARTCLOCKSTEP_RESET 0 |
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#define UARTCLOCK_ADDRESS 0x0008 |
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#define UARTCLOCK_HW_MASK 0x00ffffff |
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#define UARTCLOCK_SW_MASK 0x00ffffff |
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#define UARTCLOCK_RSTMASK 0x00ffffff |
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#define UARTCLOCK_RESET 0x00000000 |
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// 0x000c (UARTINT)
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#define UARTINT_UARTTXEMPTYINT_MSB 9 |
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#define UARTINT_UARTTXEMPTYINT_LSB 9 |
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#define UARTINT_UARTTXEMPTYINT_MASK 0x00000200 |
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#define UARTINT_UARTTXEMPTYINT_GET(x) (((x) & UARTINT_UARTTXEMPTYINT_MASK) >> UARTINT_UARTTXEMPTYINT_LSB) |
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#define UARTINT_UARTTXEMPTYINT_SET(x) (((0 | (x)) << UARTINT_UARTTXEMPTYINT_LSB) & UARTINT_UARTTXEMPTYINT_MASK) |
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#define UARTINT_UARTTXEMPTYINT_RESET 0 |
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#define UARTINT_UARTRXFULLINT_MSB 8 |
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#define UARTINT_UARTRXFULLINT_LSB 8 |
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#define UARTINT_UARTRXFULLINT_MASK 0x00000100 |
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#define UARTINT_UARTRXFULLINT_GET(x) (((x) & UARTINT_UARTRXFULLINT_MASK) >> UARTINT_UARTRXFULLINT_LSB) |
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#define UARTINT_UARTRXFULLINT_SET(x) (((0 | (x)) << UARTINT_UARTRXFULLINT_LSB) & UARTINT_UARTRXFULLINT_MASK) |
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#define UARTINT_UARTRXFULLINT_RESET 0 |
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#define UARTINT_UARTRXBREAKOFFINT_MSB 7 |
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#define UARTINT_UARTRXBREAKOFFINT_LSB 7 |
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#define UARTINT_UARTRXBREAKOFFINT_MASK 0x00000080 |
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#define UARTINT_UARTRXBREAKOFFINT_GET(x) (((x) & UARTINT_UARTRXBREAKOFFINT_MASK) >> UARTINT_UARTRXBREAKOFFINT_LSB) |
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#define UARTINT_UARTRXBREAKOFFINT_SET(x) (((0 | (x)) << UARTINT_UARTRXBREAKOFFINT_LSB) & UARTINT_UARTRXBREAKOFFINT_MASK) |
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#define UARTINT_UARTRXBREAKOFFINT_RESET 0 |
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#define UARTINT_UARTRXBREAKONINT_MSB 6 |
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#define UARTINT_UARTRXBREAKONINT_LSB 6 |
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#define UARTINT_UARTRXBREAKONINT_MASK 0x00000040 |
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#define UARTINT_UARTRXBREAKONINT_GET(x) (((x) & UARTINT_UARTRXBREAKONINT_MASK) >> UARTINT_UARTRXBREAKONINT_LSB) |
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#define UARTINT_UARTRXBREAKONINT_SET(x) (((0 | (x)) << UARTINT_UARTRXBREAKONINT_LSB) & UARTINT_UARTRXBREAKONINT_MASK) |
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#define UARTINT_UARTRXBREAKONINT_RESET 0 |
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#define UARTINT_UARTRXPARITYERRINT_MSB 5 |
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#define UARTINT_UARTRXPARITYERRINT_LSB 5 |
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#define UARTINT_UARTRXPARITYERRINT_MASK 0x00000020 |
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#define UARTINT_UARTRXPARITYERRINT_GET(x) (((x) & UARTINT_UARTRXPARITYERRINT_MASK) >> UARTINT_UARTRXPARITYERRINT_LSB) |
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#define UARTINT_UARTRXPARITYERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXPARITYERRINT_LSB) & UARTINT_UARTRXPARITYERRINT_MASK) |
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#define UARTINT_UARTRXPARITYERRINT_RESET 0 |
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#define UARTINT_UARTTXOFLOWERRINT_MSB 4 |
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#define UARTINT_UARTTXOFLOWERRINT_LSB 4 |
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#define UARTINT_UARTTXOFLOWERRINT_MASK 0x00000010 |
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#define UARTINT_UARTTXOFLOWERRINT_GET(x) (((x) & UARTINT_UARTTXOFLOWERRINT_MASK) >> UARTINT_UARTTXOFLOWERRINT_LSB) |
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#define UARTINT_UARTTXOFLOWERRINT_SET(x) (((0 | (x)) << UARTINT_UARTTXOFLOWERRINT_LSB) & UARTINT_UARTTXOFLOWERRINT_MASK) |
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#define UARTINT_UARTTXOFLOWERRINT_RESET 0 |
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#define UARTINT_UARTRXOFLOWERRINT_MSB 3 |
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#define UARTINT_UARTRXOFLOWERRINT_LSB 3 |
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#define UARTINT_UARTRXOFLOWERRINT_MASK 0x00000008 |
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#define UARTINT_UARTRXOFLOWERRINT_GET(x) (((x) & UARTINT_UARTRXOFLOWERRINT_MASK) >> UARTINT_UARTRXOFLOWERRINT_LSB) |
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#define UARTINT_UARTRXOFLOWERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXOFLOWERRINT_LSB) & UARTINT_UARTRXOFLOWERRINT_MASK) |
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#define UARTINT_UARTRXOFLOWERRINT_RESET 0 |
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#define UARTINT_UARTRXFRAMINGERRINT_MSB 2 |
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#define UARTINT_UARTRXFRAMINGERRINT_LSB 2 |
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#define UARTINT_UARTRXFRAMINGERRINT_MASK 0x00000004 |
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#define UARTINT_UARTRXFRAMINGERRINT_GET(x) (((x) & UARTINT_UARTRXFRAMINGERRINT_MASK) >> UARTINT_UARTRXFRAMINGERRINT_LSB) |
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#define UARTINT_UARTRXFRAMINGERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXFRAMINGERRINT_LSB) & UARTINT_UARTRXFRAMINGERRINT_MASK) |
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#define UARTINT_UARTRXFRAMINGERRINT_RESET 0 |
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#define UARTINT_UARTTXREADYINT_MSB 1 |
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#define UARTINT_UARTTXREADYINT_LSB 1 |
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#define UARTINT_UARTTXREADYINT_MASK 0x00000002 |
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#define UARTINT_UARTTXREADYINT_GET(x) (((x) & UARTINT_UARTTXREADYINT_MASK) >> UARTINT_UARTTXREADYINT_LSB) |
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#define UARTINT_UARTTXREADYINT_SET(x) (((0 | (x)) << UARTINT_UARTTXREADYINT_LSB) & UARTINT_UARTTXREADYINT_MASK) |
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#define UARTINT_UARTTXREADYINT_RESET 0 |
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#define UARTINT_UARTRXVALIDINT_MSB 0 |
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#define UARTINT_UARTRXVALIDINT_LSB 0 |
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#define UARTINT_UARTRXVALIDINT_MASK 0x00000001 |
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#define UARTINT_UARTRXVALIDINT_GET(x) (((x) & UARTINT_UARTRXVALIDINT_MASK) >> UARTINT_UARTRXVALIDINT_LSB) |
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#define UARTINT_UARTRXVALIDINT_SET(x) (((0 | (x)) << UARTINT_UARTRXVALIDINT_LSB) & UARTINT_UARTRXVALIDINT_MASK) |
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#define UARTINT_UARTRXVALIDINT_RESET 0 |
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#define UARTINT_ADDRESS 0x000c |
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#define UARTINT_HW_MASK 0x000003ff |
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#define UARTINT_SW_MASK 0x000003ff |
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#define UARTINT_RSTMASK 0x000003ff |
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#define UARTINT_RESET 0x00000000 |
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// 0x0010 (UARTINTEN)
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#define UARTINTEN_UARTTXEMPTYINTEN_MSB 9 |
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#define UARTINTEN_UARTTXEMPTYINTEN_LSB 9 |
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#define UARTINTEN_UARTTXEMPTYINTEN_MASK 0x00000200 |
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#define UARTINTEN_UARTTXEMPTYINTEN_GET(x) (((x) & UARTINTEN_UARTTXEMPTYINTEN_MASK) >> UARTINTEN_UARTTXEMPTYINTEN_LSB) |
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#define UARTINTEN_UARTTXEMPTYINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXEMPTYINTEN_LSB) & UARTINTEN_UARTTXEMPTYINTEN_MASK) |
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#define UARTINTEN_UARTTXEMPTYINTEN_RESET 0 |
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#define UARTINTEN_UARTRXFULLINTEN_MSB 8 |
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#define UARTINTEN_UARTRXFULLINTEN_LSB 8 |
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#define UARTINTEN_UARTRXFULLINTEN_MASK 0x00000100 |
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#define UARTINTEN_UARTRXFULLINTEN_GET(x) (((x) & UARTINTEN_UARTRXFULLINTEN_MASK) >> UARTINTEN_UARTRXFULLINTEN_LSB) |
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#define UARTINTEN_UARTRXFULLINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXFULLINTEN_LSB) & UARTINTEN_UARTRXFULLINTEN_MASK) |
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#define UARTINTEN_UARTRXFULLINTEN_RESET 0 |
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#define UARTINTEN_UARTRXBREAKOFFINTEN_MSB 7 |
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#define UARTINTEN_UARTRXBREAKOFFINTEN_LSB 7 |
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#define UARTINTEN_UARTRXBREAKOFFINTEN_MASK 0x00000080 |
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#define UARTINTEN_UARTRXBREAKOFFINTEN_GET(x) (((x) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK) >> UARTINTEN_UARTRXBREAKOFFINTEN_LSB) |
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#define UARTINTEN_UARTRXBREAKOFFINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXBREAKOFFINTEN_LSB) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK) |
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#define UARTINTEN_UARTRXBREAKOFFINTEN_RESET 0 |
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#define UARTINTEN_UARTRXBREAKONINTEN_MSB 6 |
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#define UARTINTEN_UARTRXBREAKONINTEN_LSB 6 |
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#define UARTINTEN_UARTRXBREAKONINTEN_MASK 0x00000040 |
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#define UARTINTEN_UARTRXBREAKONINTEN_GET(x) (((x) & UARTINTEN_UARTRXBREAKONINTEN_MASK) >> UARTINTEN_UARTRXBREAKONINTEN_LSB) |
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#define UARTINTEN_UARTRXBREAKONINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXBREAKONINTEN_LSB) & UARTINTEN_UARTRXBREAKONINTEN_MASK) |
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#define UARTINTEN_UARTRXBREAKONINTEN_RESET 0 |
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#define UARTINTEN_UARTRXPARITYERRINTEN_MSB 5 |
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#define UARTINTEN_UARTRXPARITYERRINTEN_LSB 5 |
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#define UARTINTEN_UARTRXPARITYERRINTEN_MASK 0x00000020 |
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#define UARTINTEN_UARTRXPARITYERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXPARITYERRINTEN_MASK) >> UARTINTEN_UARTRXPARITYERRINTEN_LSB) |
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#define UARTINTEN_UARTRXPARITYERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXPARITYERRINTEN_LSB) & UARTINTEN_UARTRXPARITYERRINTEN_MASK) |
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#define UARTINTEN_UARTRXPARITYERRINTEN_RESET 0 |
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#define UARTINTEN_UARTTXOFLOWERRINTEN_MSB 4 |
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#define UARTINTEN_UARTTXOFLOWERRINTEN_LSB 4 |
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#define UARTINTEN_UARTTXOFLOWERRINTEN_MASK 0x00000010 |
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#define UARTINTEN_UARTTXOFLOWERRINTEN_GET(x) (((x) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTTXOFLOWERRINTEN_LSB) |
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#define UARTINTEN_UARTTXOFLOWERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXOFLOWERRINTEN_LSB) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK) |
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#define UARTINTEN_UARTTXOFLOWERRINTEN_RESET 0 |
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#define UARTINTEN_UARTRXOFLOWERRINTEN_MSB 3 |
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#define UARTINTEN_UARTRXOFLOWERRINTEN_LSB 3 |
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#define UARTINTEN_UARTRXOFLOWERRINTEN_MASK 0x00000008 |
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#define UARTINTEN_UARTRXOFLOWERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTRXOFLOWERRINTEN_LSB) |
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#define UARTINTEN_UARTRXOFLOWERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXOFLOWERRINTEN_LSB) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK) |
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#define UARTINTEN_UARTRXOFLOWERRINTEN_RESET 0 |
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#define UARTINTEN_UARTRXFRAMINGERRINTEN_MSB 2 |
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#define UARTINTEN_UARTRXFRAMINGERRINTEN_LSB 2 |
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#define UARTINTEN_UARTRXFRAMINGERRINTEN_MASK 0x00000004 |
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#define UARTINTEN_UARTRXFRAMINGERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK) >> UARTINTEN_UARTRXFRAMINGERRINTEN_LSB) |
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#define UARTINTEN_UARTRXFRAMINGERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXFRAMINGERRINTEN_LSB) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK) |
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#define UARTINTEN_UARTRXFRAMINGERRINTEN_RESET 0 |
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#define UARTINTEN_UARTTXREADYINTEN_MSB 1 |
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#define UARTINTEN_UARTTXREADYINTEN_LSB 1 |
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#define UARTINTEN_UARTTXREADYINTEN_MASK 0x00000002 |
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#define UARTINTEN_UARTTXREADYINTEN_GET(x) (((x) & UARTINTEN_UARTTXREADYINTEN_MASK) >> UARTINTEN_UARTTXREADYINTEN_LSB) |
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#define UARTINTEN_UARTTXREADYINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXREADYINTEN_LSB) & UARTINTEN_UARTTXREADYINTEN_MASK) |
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#define UARTINTEN_UARTTXREADYINTEN_RESET 0 |
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#define UARTINTEN_UARTRXVALIDINTEN_MSB 0 |
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#define UARTINTEN_UARTRXVALIDINTEN_LSB 0 |
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#define UARTINTEN_UARTRXVALIDINTEN_MASK 0x00000001 |
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#define UARTINTEN_UARTRXVALIDINTEN_GET(x) (((x) & UARTINTEN_UARTRXVALIDINTEN_MASK) >> UARTINTEN_UARTRXVALIDINTEN_LSB) |
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#define UARTINTEN_UARTRXVALIDINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXVALIDINTEN_LSB) & UARTINTEN_UARTRXVALIDINTEN_MASK) |
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#define UARTINTEN_UARTRXVALIDINTEN_RESET 0 |
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#define UARTINTEN_ADDRESS 0x0010 |
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#define UARTINTEN_HW_MASK 0x000003ff |
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#define UARTINTEN_SW_MASK 0x000003ff |
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#define UARTINTEN_RSTMASK 0x000003ff |
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#define UARTINTEN_RESET 0x00000000 |
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/*
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* uncomment below to enable WAR for EV81847. |
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*/ |
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@ -406,8 +142,8 @@ static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up, |
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static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up) |
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{ |
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ar933x_uart_rmw_set(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTTXEMPTYINTEN_SET(1)); |
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ar933x_uart_rmw_set(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_TX_EMPTY); |
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} |
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static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up) |
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@ -416,8 +152,8 @@ static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up) |
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up->ier &= ~UART_IER_THRI; |
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/* FIXME: why this uses RXVALIDINTEN? */ |
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ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTRXVALIDINTEN_SET(1)); |
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ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_RX_VALID); |
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} |
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} |
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@ -428,10 +164,10 @@ static unsigned int ar933x_uart_tx_empty(struct uart_port *port) |
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unsigned int rdata; |
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spin_lock_irqsave(&up->port.lock, flags); |
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rdata = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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spin_unlock_irqrestore(&up->port.lock, flags); |
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return (rdata & UARTDATA_UARTTXCSR_MASK) ? 0 : TIOCSER_TEMT; |
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return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT; |
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} |
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static unsigned int ar933x_uart_get_mctrl(struct uart_port *port) |
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@ -464,8 +200,8 @@ static void ar933x_uart_stop_rx(struct uart_port *port) |
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up->ier &= ~UART_IER_RLSI; |
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up->port.read_status_mask &= ~UART_LSR_DR; |
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ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTRXVALIDINTEN_SET(1)); |
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ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_RX_VALID); |
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} |
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static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) |
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@ -481,13 +217,13 @@ static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) |
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else |
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up->lcr &= ~UART_LCR_SBC; |
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rdata = ar933x_uart_read(up, UARTCS_ADDRESS); |
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rdata = ar933x_uart_read(up, AR933X_UART_CS_REG); |
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if (up->lcr & UART_LCR_SBC) |
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rdata |= UARTCS_UARTTXBREAK_SET(1); |
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rdata |= AR933X_UART_CS_TX_BREAK; |
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else |
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rdata &= ~UARTCS_UARTTXBREAK_SET(1); |
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rdata &= ~AR933X_UART_CS_TX_BREAK; |
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ar933x_uart_write(up, UARTCS_ADDRESS, rdata); |
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ar933x_uart_write(up, AR933X_UART_CS_REG, rdata); |
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spin_unlock_irqrestore(&up->port.lock, flags); |
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} |
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@ -613,8 +349,8 @@ static void ar933x_uart_set_termios(struct uart_port *port, |
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if (UART_ENABLE_MS(&up->port, termios->c_cflag)) |
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up->ier |= UART_IER_MSI; |
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ar933x_uart_rmw_set(up, UARTCS_ADDRESS, |
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UARTCS_UARTHOSTINTEN_SET(1)); |
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ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, |
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AR933X_UART_CS_HOST_INT_EN); |
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/* Save LCR */ |
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up->lcr = cval; |
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@ -632,13 +368,13 @@ static void ar933x_uart_rx_chars(struct ar933x_uart_port *up, int *status) |
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char flag; |
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do { |
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ch = (unsigned char)UARTDATA_UARTTXRXDATA_GET(lsr); |
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ch = lsr & AR933X_UART_DATA_TX_RX_MASK; |
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flag = TTY_NORMAL; |
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up->port.icount.rx++; |
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lsr = UARTDATA_UARTRXCSR_SET(1); |
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ar933x_uart_write(up, UARTDATA_ADDRESS, lsr); |
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lsr = AR933X_UART_DATA_RX_CSR; |
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ar933x_uart_write(up, AR933X_UART_DATA_REG, lsr); |
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if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | |
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UART_LSR_FE | UART_LSR_OE))) { |
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@ -683,8 +419,8 @@ static void ar933x_uart_rx_chars(struct ar933x_uart_port *up, int *status) |
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uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); |
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ignore_char: |
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lsr = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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} while ((lsr & UARTDATA_UARTRXCSR_MASK) && (max_count-- > 0)); |
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lsr = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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} while ((lsr & AR933X_UART_DATA_RX_CSR) && (max_count-- > 0)); |
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spin_unlock(&up->port.lock); |
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tty_flip_buffer_push(tty); |
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@ -699,16 +435,16 @@ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) |
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int count; |
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unsigned int rdata; |
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rdata = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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if (UARTDATA_UARTTXCSR_GET(rdata) == 0) { |
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rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) { |
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ar933x_uart_start_tx_interrupt(up); |
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return; |
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} |
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if (up->port.x_char) { |
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rdata = UARTDATA_UARTTXRXDATA_SET((unsigned int)(up->port.x_char)); |
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rdata |= UARTDATA_UARTTXCSR_SET(1); |
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ar933x_uart_write(up, UARTDATA_ADDRESS, rdata); |
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rdata = up->port.x_char & AR933X_UART_DATA_TX_RX_MASK; |
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rdata |= AR933X_UART_DATA_TX_CSR; |
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ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); |
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up->port.icount.tx++; |
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up->port.x_char = 0; |
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ar933x_uart_start_tx_interrupt(up); |
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@ -727,15 +463,15 @@ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) |
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count = up->port.fifosize / 4; |
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do { |
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rdata = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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if (UARTDATA_UARTTXCSR_GET(rdata) == 0) { |
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rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) { |
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ar933x_uart_start_tx_interrupt(up); |
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return; |
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} |
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rdata = UARTDATA_UARTTXRXDATA_SET((unsigned int)(xmit->buf[xmit->tail])); |
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rdata |= UARTDATA_UARTTXCSR_SET(1); |
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ar933x_uart_write(up, UARTDATA_ADDRESS, rdata); |
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rdata = xmit->buf[xmit->tail] & AR933X_UART_DATA_TX_RX_MASK; |
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rdata |= AR933X_UART_DATA_TX_CSR; |
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ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); |
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
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up->port.icount.tx++; |
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@ -743,8 +479,8 @@ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) |
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break; |
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} while (--count > 0); |
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rdata = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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if (UARTDATA_UARTTXCSR_GET(rdata) == 0) { |
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rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) { |
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ar933x_uart_start_tx_interrupt(up); |
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return; |
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} |
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@ -778,26 +514,26 @@ static inline void ar933x_uart_clear_int(struct ar933x_uart_port *up) |
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//ar7240_reg_rmw_clear(AR7240_MISC_INT_MASK, BIT3);
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/* 2. clear uartcs hostinten mask, bit13 */ |
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ar933x_uart_rmw_clear(up, UARTCS_ADDRESS, |
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UARTCS_UARTHOSTINTEN_SET(1)); |
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ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, |
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AR933X_UART_CS_HOST_INT_EN); |
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/* 3. clear rx uartint */ |
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ar933x_uart_write(up, UARTINT_ADDRESS, UARTINT_UARTRXVALIDINT_SET(1)); |
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ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID); |
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/* 4. clear misc interrupt status */ |
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ar7240_reg_rmw_clear(AR7240_MISC_INT_STATUS, BIT3); |
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/* 5. clear rx uartinten*/ |
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ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTRXVALIDINTEN_SET(1)); |
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ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_RX_VALID); |
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/* 6. enable rx int*/ |
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ar933x_uart_rmw_set(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTRXVALIDINTEN_SET(1)); |
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ar933x_uart_rmw_set(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_RX_VALID); |
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/* 7. set uartcs hostinten mask */ |
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ar933x_uart_rmw_set(up, UARTCS_ADDRESS, |
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UARTCS_UARTHOSTINTEN_SET(1)); |
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ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, |
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AR933X_UART_CS_HOST_INT_EN); |
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/* 8. set misc int mask */ |
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//ar7240_reg_wr(AR7240_MISC_INT_MASK, BIT3);
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@ -810,23 +546,23 @@ static inline void ar933x_uart_handle_port(struct ar933x_uart_port *up) |
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unsigned int en_status; |
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unsigned long flags; |
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status = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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int_status = ar933x_uart_read(up, UARTINT_ADDRESS); |
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en_status = ar933x_uart_read(up, UARTINTEN_ADDRESS); |
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status = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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int_status = ar933x_uart_read(up, AR933X_UART_INT_REG); |
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en_status = ar933x_uart_read(up, AR933X_UART_INT_EN_REG); |
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spin_lock_irqsave(&up->port.lock, flags); |
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if( (int_status & en_status) & UARTINT_UARTRXVALIDINT_MASK ) |
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if( (int_status & en_status) & AR933X_UART_INT_RX_VALID ) |
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ar933x_uart_rx_chars(up, &status); |
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if (((int_status & en_status) & UARTINT_UARTTXEMPTYINT_MASK)) { |
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if (((int_status & en_status) & AR933X_UART_INT_TX_EMPTY)) { |
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/* clear TX empty interrupts */ |
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ar933x_uart_write(up, UARTINT_ADDRESS, |
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UARTINT_UARTTXEMPTYINT_SET(1)); |
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ar933x_uart_write(up, AR933X_UART_INT_REG, |
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AR933X_UART_INT_TX_EMPTY); |
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/* disable TX empty interrupts */ |
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ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTTXEMPTYINTEN_SET(1)); |
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ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_TX_EMPTY); |
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if (!uart_circ_empty(&up->port.state->xmit)) |
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ar933x_uart_tx_chars(up); |
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@ -842,8 +578,8 @@ static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id) |
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up = (struct ar933x_uart_port *) dev_id; |
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iir = ar933x_uart_read(up, UARTCS_ADDRESS); |
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if ((iir & UARTCS_UARTHOSTINT_MASK) == 0) |
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iir = ar933x_uart_read(up, AR933X_UART_CS_REG); |
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if ((iir & AR933X_UART_CS_HOST_INT) == 0) |
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return IRQ_NONE; |
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DEBUG_INTR("ar933x_uart_interrupt(%d)...", irq); |
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@ -874,8 +610,8 @@ static void ar933x_uart_timer(unsigned long data) |
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spin_unlock_irqrestore(&up->port.lock, flags); |
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} |
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} else { |
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iir = ar933x_uart_read(up, UARTCS_ADDRESS); |
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if (iir & UARTCS_UARTHOSTINT_MASK) { |
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iir = ar933x_uart_read(up, AR933X_UART_CS_REG); |
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if (iir & AR933X_UART_CS_HOST_INT) { |
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spin_lock(&up->port.lock); |
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ar933x_uart_handle_port(up); |
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spin_unlock(&up->port.lock); |
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@ -901,8 +637,8 @@ static int ar933x_uart_startup(struct uart_port *port) |
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/*
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* Clear the interrupt registers. |
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*/ |
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ar933x_uart_read(up, UARTCS_ADDRESS); |
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ar933x_uart_read(up, UARTINT_ADDRESS); |
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ar933x_uart_read(up, AR933X_UART_CS_REG); |
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ar933x_uart_read(up, AR933X_UART_INT_REG); |
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if (!is_real_interrupt(up->port.irq) || ar933x_ev81847_war()) { |
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setup_timer(&up->timer, ar933x_uart_timer, (unsigned long)port); |
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@ -915,20 +651,20 @@ static int ar933x_uart_startup(struct uart_port *port) |
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/*
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* Enable host interrupts |
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*/ |
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ar933x_uart_rmw_set(up, UARTCS_ADDRESS, |
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UARTCS_UARTHOSTINTEN_SET(1)); |
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ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, |
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AR933X_UART_CS_HOST_INT_EN); |
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/*
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* Enable RX interrupts |
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*/ |
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up->ier = UART_IER_RLSI | UART_IER_RDI; |
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ar933x_uart_write(up, UARTINTEN_ADDRESS, |
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UARTINTEN_UARTRXVALIDINTEN_SET(1)); |
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ar933x_uart_write(up, AR933X_UART_INT_EN_REG, |
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AR933X_UART_INT_RX_VALID); |
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/*
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* And clear the interrupt registers again for luck. |
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*/ |
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ar933x_uart_read(up, UARTINT_ADDRESS); |
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ar933x_uart_read(up, AR933X_UART_INT_REG); |
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spin_unlock_irqrestore(&up->port.lock, flags); |
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@ -944,7 +680,7 @@ static void ar933x_uart_shutdown(struct uart_port *port) |
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* Disable all interrupts from this port |
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*/ |
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up->ier = 0; |
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ar933x_uart_write(up, UARTINTEN_ADDRESS, 0); |
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ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0); |
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spin_lock_irqsave(&up->port.lock, flags); |
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|
up->port.mctrl &= ~TIOCM_OUT2; |
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|
@ -954,8 +690,8 @@ static void ar933x_uart_shutdown(struct uart_port *port) |
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|
/*
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|
* Disable break condition |
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|
*/ |
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|
ar933x_uart_rmw_clear(up, UARTCS_ADDRESS, |
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|
|
UARTCS_UARTTXBREAK_SET(1)); |
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ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, |
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|
AR933X_UART_CS_TX_BREAK); |
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|
if (!is_real_interrupt(up->port.irq) || |
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|
|
ar933x_ev81847_war()) |
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|
@ -987,9 +723,9 @@ static void ar933x_uart_config_port(struct uart_port *port, int flags) |
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|
port->type = PORT_AR933X; |
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|
/* Clear mask, so no surprise interrupts. */ |
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|
ar933x_uart_read(up, UARTCS_ADDRESS); |
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|
ar933x_uart_read(up, AR933X_UART_CS_REG); |
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|
|
/* Clear interrupts status register */ |
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|
|
ar933x_uart_read(up, UARTINT_ADDRESS); |
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|
|
ar933x_uart_read(up, AR933X_UART_INT_REG); |
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|
|
} |
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|
|
static int ar933x_uart_verify_port(struct uart_port *port, |
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|
@ -1028,11 +764,11 @@ static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up) |
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|
|
/* Wait up to 60ms for the character(s) to be sent. */ |
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|
|
do { |
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|
|
status = ar933x_uart_read(up, UARTDATA_ADDRESS); |
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|
|
status = ar933x_uart_read(up, AR933X_UART_DATA_REG); |
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|
|
if (--timeout == 0) |
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|
|
break; |
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|
|
udelay(1); |
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|
|
} while (UARTDATA_UARTTXCSR_GET(status) == 0); |
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|
|
} while ((status & AR933X_UART_DATA_TX_CSR) == 0); |
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|
|
} |
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|
static void ar933x_uart_console_putchar(struct uart_port *port, int ch) |
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|
@ -1042,9 +778,9 @@ static void ar933x_uart_console_putchar(struct uart_port *port, int ch) |
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|
|
ar933x_uart_wait_xmitr(up); |
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|
|
rdata = UARTDATA_UARTTXRXDATA_SET(ch) | |
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|
|
UARTDATA_UARTTXCSR_SET(1); |
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|
|
ar933x_uart_write(up, UARTDATA_ADDRESS, rdata); |
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|
|
rdata = ch & AR933X_UART_DATA_TX_RX_MASK; |
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|
|
rdata |= AR933X_UART_DATA_TX_CSR; |
|
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|
|
ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); |
|
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|
|
} |
|
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|
|
static void ar933x_uart_console_write(struct console *co, const char *s, |
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|
|
@ -1067,8 +803,8 @@ static void ar933x_uart_console_write(struct console *co, const char *s, |
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|
|
|
/*
|
|
|
|
|
* First save the IER then disable the interrupts |
|
|
|
|
*/ |
|
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|
|
ier = ar933x_uart_read(up, UARTINTEN_ADDRESS); |
|
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|
|
ar933x_uart_write(up, UARTINTEN_ADDRESS, 0); |
|
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|
|
ier = ar933x_uart_read(up, AR933X_UART_INT_EN_REG); |
|
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|
|
ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0); |
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|
|
uart_console_write(&up->port, s, count, ar933x_uart_console_putchar); |
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|
|
@ -1078,8 +814,8 @@ static void ar933x_uart_console_write(struct console *co, const char *s, |
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|
|
*/ |
|
|
|
|
ar933x_uart_wait_xmitr(up); |
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|
|
ar933x_uart_write(up, UARTINTEN_ADDRESS, ier); |
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|
|
ar933x_uart_write(up, UARTINT_ADDRESS, UARTINT_RSTMASK); |
|
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|
|
ar933x_uart_write(up, AR933X_UART_INT_EN_REG, ier); |
|
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|
|
ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS); |
|
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|
|
if (locked) |
|
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|
|
spin_unlock(&up->port.lock); |
|
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|
|