Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 39329master
parent
a75b692557
commit
a818a3cf8f
@ -0,0 +1,49 @@ |
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From 553ddf4f3f20c28ab03f87ac8c3cde5edf714675 Mon Sep 17 00:00:00 2001
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From: Tony Wu <tung7970@gmail.com>
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Date: Fri, 21 Jun 2013 10:13:08 +0000
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Subject: [PATCH 022/105] MIPS: GIC: Fix gic_set_affinity infinite loop
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There is an infinite loop in gic_set_affinity. When irq_set_affinity
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gets called on gic controller, it blocks forever.
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Signed-off-by: Tony Wu <tung7970@gmail.com>
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Cc: Steven J. Hill <Steven.Hill@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/5537/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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(cherry picked from commit c214c03512b67e56dea3f4471705f8caae49553a)
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---
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arch/mips/kernel/irq-gic.c | 15 +++++++--------
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1 file changed, 7 insertions(+), 8 deletions(-)
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diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
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index c01b307..5b5ddb2 100644
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--- a/arch/mips/kernel/irq-gic.c
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+++ b/arch/mips/kernel/irq-gic.c
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@@ -219,16 +219,15 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
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/* Assumption : cpumask refers to a single CPU */
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spin_lock_irqsave(&gic_lock, flags);
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- for (;;) {
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- /* Re-route this IRQ */
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- GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
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- /* Update the pcpu_masks */
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- for (i = 0; i < NR_CPUS; i++)
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- clear_bit(irq, pcpu_masks[i].pcpu_mask);
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- set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
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+ /* Re-route this IRQ */
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+ GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
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+
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+ /* Update the pcpu_masks */
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+ for (i = 0; i < NR_CPUS; i++)
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+ clear_bit(irq, pcpu_masks[i].pcpu_mask);
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+ set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
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- }
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cpumask_copy(d->affinity, cpumask);
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spin_unlock_irqrestore(&gic_lock, flags);
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--
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1.7.10.4
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@ -0,0 +1,57 @@ |
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From 184edf882ebb7885b49fa231a503205da94e78f0 Mon Sep 17 00:00:00 2001
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From: Markos Chandras <markos.chandras@imgtec.com>
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Date: Wed, 2 Oct 2013 12:40:26 -0500
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Subject: [PATCH 065/105] MIPS: Kconfig: CMP support needs to select SMP as
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well
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The CMP code is only designed to work with SMP configurations.
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Fixes multiple build problems on certain randconfigs:
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In file included from arch/mips/kernel/smp-cmp.c:34:0:
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arch/mips/include/asm/smp.h:28:0:
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error: "raw_smp_processor_id" redefined [-Werror]
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In file included from include/linux/sched.h:30:0,
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from arch/mips/kernel/smp-cmp.c:22:
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include/linux/smp.h:135:0: note: this is the location of the
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previous definition
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In file included from arch/mips/kernel/smp-cmp.c:34:0:
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arch/mips/include/asm/smp.h:57:20:
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error: redefinition of 'smp_send_reschedule'
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In file included from include/linux/sched.h:30:0,
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from arch/mips/kernel/smp-cmp.c:22:
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include/linux/smp.h:179:20: note: previous
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definition of 'smp_send_reschedule' was here
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In file included from arch/mips/kernel/smp-cmp.c:34:0:
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arch/mips/include/asm/smp.h: In function 'smp_send_reschedule':
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arch/mips/include/asm/smp.h:61:8:
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error: dereferencing pointer to incomplete type
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[...]
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Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Cc: Markos Chandras <markos.chandras@imgtec.com>
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Patchwork: https://patchwork.linux-mips.org/patch/5812/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/Kconfig | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
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index e82c066..b537fb1 100644
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -2010,6 +2010,7 @@ config MIPS_VPE_APSP_API
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config MIPS_CMP
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bool "MIPS CMP framework support"
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depends on SYS_SUPPORTS_MIPS_CMP
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+ select SMP
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select SYNC_R4K
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select SYS_SUPPORTS_SMP
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select SYS_SUPPORTS_SCHED_SMT if SMP
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--
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1.7.10.4
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From c4d621e75e865fa5374946515ad0c5e060b9c446 Mon Sep 17 00:00:00 2001
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From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
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Date: Wed, 11 Sep 2013 14:17:47 -0500
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Subject: [PATCH 056/105] MIPS: Fix SMP core calculations when using MT
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support.
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The TCBIND register is only available if the core has MT support. It
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should not be read otherwise. Secondly, the number of TCs (siblings)
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are calculated differently depending on if the kernel is configured
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as SMVP or SMTC.
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Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
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Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/5822/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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(cherry picked from commit 670bac3a8c201fc1f5f92ac6b4a8b42dc8172937)
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---
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arch/mips/kernel/smp-cmp.c | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
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index c2e5d74..5969f1e 100644
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--- a/arch/mips/kernel/smp-cmp.c
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+++ b/arch/mips/kernel/smp-cmp.c
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@@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
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c->core = (read_c0_ebase() >> 1) & 0x1ff;
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#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
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- c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
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+ if (cpu_has_mipsmt)
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+ c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
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+ TCBIND_CURVPE;
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
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@@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
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}
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if (cpu_has_mipsmt) {
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- unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
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+ unsigned int nvpe = 1;
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+#ifdef CONFIG_MIPS_MT_SMP
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+ unsigned int mvpconf0 = read_c0_mvpconf0();
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+
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+ nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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+#elif defined(CONFIG_MIPS_MT_SMTC)
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+ unsigned int mvpconf0 = read_c0_mvpconf0();
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nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
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+#endif
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smp_num_siblings = nvpe;
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}
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pr_info("Detected %i available secondary CPU(s)\n", ncpu);
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--
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1.7.10.4
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From 43334f8438704001deb258b6e7223699bd336c77 Mon Sep 17 00:00:00 2001
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From: "Steven J. Hill" <Steven.Hill@imgtec.com>
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Date: Wed, 25 Sep 2013 14:58:19 -0500
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Subject: [PATCH 093/105] MIPS: GIC: Send IPIs using the GIC.
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If a GIC present, then use it to send IPIs between the cores.
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Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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---
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arch/mips/kernel/smp-mt.c | 32 ++++++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
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index 2f8c468..d057c84 100644
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--- a/arch/mips/kernel/smp-mt.c
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+++ b/arch/mips/kernel/smp-mt.c
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@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
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/* Record this as available CPU */
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set_cpu_possible(tc, true);
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+ set_cpu_present(tc, true);
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__cpu_number_map[tc] = ++ncpu;
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__cpu_logical_map[ncpu] = tc;
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}
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@@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
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write_tc_c0_tchalt(TCHALT_H);
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}
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+static void mp_send_ipi_single(int cpu, unsigned int action)
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+{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+
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+ switch (action) {
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+ case SMP_CALL_FUNCTION:
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+ gic_send_ipi(plat_ipi_call_int_xlate(cpu));
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+ break;
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+
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+ case SMP_RESCHEDULE_YOURSELF:
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+ gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
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+ break;
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+ }
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+
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+ local_irq_restore(flags);
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+}
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+
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static void vsmp_send_ipi_single(int cpu, unsigned int action)
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{
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int i;
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unsigned long flags;
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int vpflags;
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+ if (gic_present) {
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+ mp_send_ipi_single(cpu, action);
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+ return;
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+ }
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local_irq_save(flags);
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vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
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@@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondary(void)
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static void __cpuinit vsmp_smp_finish(void)
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{
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+ pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id());
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+
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/* CDFIXME: remove this? */
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write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
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@@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(void)
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static void vsmp_cpus_done(void)
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{
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+ pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id());
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}
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/*
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@@ -191,6 +218,8 @@ static void vsmp_cpus_done(void)
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static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
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{
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struct thread_info *gp = task_thread_info(idle);
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+ pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n",
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+ smp_processor_id(), cpu);
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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@@ -232,6 +261,7 @@ static void __init vsmp_smp_setup(void)
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unsigned int mvpconf0, ntc, tc, ncpu = 0;
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unsigned int nvpe;
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+ pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id());
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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@@ -272,6 +302,8 @@ static void __init vsmp_smp_setup(void)
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static void __init vsmp_prepare_cpus(unsigned int max_cpus)
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{
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+ pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n",
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+ smp_processor_id(), max_cpus);
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mips_mt_set_cpuoptions();
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}
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--
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1.7.10.4
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