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@ -289,6 +289,16 @@ static void ar71xx_set_pll_ge1(int speed) |
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val, AR71XX_ETH1_PLL_SHIFT); |
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} |
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static void ar724x_set_pll_ge0(int speed) |
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{ |
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/* TODO */ |
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} |
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static void ar724x_set_pll_ge1(int speed) |
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{ |
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/* TODO */ |
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} |
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static void ar91xx_set_pll_ge0(int speed) |
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{ |
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u32 val = ar71xx_get_eth_pll(0, speed); |
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@ -315,6 +325,16 @@ static void ar71xx_ddr_flush_ge1(void) |
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); |
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} |
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static void ar724x_ddr_flush_ge0(void) |
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{ |
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ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); |
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} |
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static void ar724x_ddr_flush_ge1(void) |
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{ |
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ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); |
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} |
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static void ar91xx_ddr_flush_ge0(void) |
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{ |
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); |
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@ -405,6 +425,10 @@ static struct platform_device ar71xx_eth1_device = { |
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#define AR71XX_PLL_VAL_100 0x00001099 |
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#define AR71XX_PLL_VAL_10 0x00991099 |
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#define AR724X_PLL_VAL_1000 0x00110000 |
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#define AR724X_PLL_VAL_100 0x00001099 |
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#define AR724X_PLL_VAL_10 0x00991099 |
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#define AR91XX_PLL_VAL_1000 0x1a000000 |
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#define AR91XX_PLL_VAL_100 0x13000a44 |
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#define AR91XX_PLL_VAL_10 0x00441099 |
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@ -433,6 +457,13 @@ static void __init ar71xx_init_eth_pll_data(unsigned int id) |
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pll_100 = AR71XX_PLL_VAL_100; |
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pll_1000 = AR71XX_PLL_VAL_1000; |
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break; |
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case AR71XX_SOC_AR7240: |
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pll_10 = AR724X_PLL_VAL_10; |
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pll_100 = AR724X_PLL_VAL_100; |
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pll_1000 = AR724X_PLL_VAL_1000; |
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break; |
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case AR71XX_SOC_AR9130: |
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case AR71XX_SOC_AR9132: |
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pll_10 = AR91XX_PLL_VAL_10; |
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@ -522,6 +553,14 @@ void __init ar71xx_add_device_eth(unsigned int id) |
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pdata->has_gbit = 1; |
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break; |
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case AR71XX_SOC_AR7240: |
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pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 |
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: ar724x_ddr_flush_ge0; |
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pdata->set_pll = id ? ar724x_set_pll_ge1 |
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: ar724x_set_pll_ge0; |
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pdata->is_ar724x = 1; |
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break; |
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case AR71XX_SOC_AR9130: |
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pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 |
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: ar91xx_ddr_flush_ge0; |
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