John Crispin
16 years ago
parent
9be32c744b
commit
9e6c38917c
@ -0,0 +1,19 @@ |
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Index: madwifi-trunk-r3314/ath/if_ath_pci.c
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===================================================================
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--- madwifi-trunk-r3314.orig/ath/if_ath_pci.c 2008-07-06 01:38:57.000000000 +0200
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+++ madwifi-trunk-r3314/ath/if_ath_pci.c 2008-07-06 01:52:09.000000000 +0200
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@@ -114,11 +114,13 @@
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{ 0x168c, 0x0023, PCI_ANY_ID, PCI_ANY_ID },
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{ 0x168c, 0x0024, PCI_ANY_ID, PCI_ANY_ID },
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{ 0x168c, 0x9013, PCI_ANY_ID, PCI_ANY_ID }, /* sonicwall */
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+ { 0x168c, 0xff1a, PCI_ANY_ID, PCI_ANY_ID },
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{ 0 }
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};
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static u16 ath_devidmap[][2] = {
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- { 0x9013, 0x0013 }
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+ { 0x9013, 0x0013 },
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+ { 0xff1a, 0x001a }
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};
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static int
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@ -0,0 +1,100 @@ |
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Index: madwifi-trunk-r3314/ath_hal/ah_os.c
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===================================================================
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--- madwifi-trunk-r3314.orig/ath_hal/ah_os.c 2008-07-06 02:42:52.000000000 +0200
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+++ madwifi-trunk-r3314/ath_hal/ah_os.c 2008-07-06 02:51:53.000000000 +0200
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@@ -343,6 +343,46 @@
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* NB: see the comments in ah_osdep.h about byte-swapping register
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* reads and writes to understand what's going on below.
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*/
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+
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+#ifdef CONFIG_IFXMIPS
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+extern int ifxmips_has_brn_block(void);
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+static int ifxmips_emulate = 0;
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+#define EEPROM_EMULATION 1
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+#endif
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+
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+#ifdef EEPROM_EMULATION
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+static int ath_hal_eeprom(struct ath_hal *ah, unsigned long addr, int val, int write)
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+{
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+ static int addrsel = 0;
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+ static int rc = 0;
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+
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+ if (write) {
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+ if(addr == 0x6000) {
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+ addrsel = val * 2;
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+ rc = 0;
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+ }
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+ } else {
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+ switch(addr)
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+ {
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+ case 0x600c:
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+ if(rc++ < 2)
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+ val = 0x00000000;
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+ else
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+ val = 0x00000002;
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+ break;
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+ case 0x6004:
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+ val = cpu_to_le16(__raw_readw((u16 *) KSEG1ADDR(0xb07f0400 + addrsel)));
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+ /* this forces the regdomain to 0x00 (worldwide), as the original setting
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+ * causes issues with the HAL */
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+ if (addrsel == 0x17e)
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+ val = 0;
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+ break;
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+ }
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+ }
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+ return val;
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+}
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+#endif
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+
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void __ahdecl
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ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val)
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{
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@@ -351,20 +391,33 @@
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ath_hal_printf(ah, "%s: WRITE 0x%x <= 0x%x\n",
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(ath_hal_func ?: "unknown"), reg, val);
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#endif
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- _OS_REG_WRITE(ah, reg, val);
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+#ifdef EEPROM_EMULATION
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+ if((reg >= 0x6000) && (reg <= 0x6010) && ifxmips_emulate)
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+ {
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+ val = ath_hal_eeprom(ah, reg, val, 1);
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+ } else
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+#endif
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+ _OS_REG_WRITE(ah, reg, val);
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}
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EXPORT_SYMBOL(ath_hal_reg_write);
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+
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/* This should only be called while holding the lock, sc->sc_hal_lock. */
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u_int32_t __ahdecl
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ath_hal_reg_read(struct ath_hal *ah, u_int reg)
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{
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- u_int32_t val;
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+ u_int32_t val;
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+#ifdef EEPROM_EMULATION
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+ if((reg >= 0x6000) && (reg <= 0x6010) && ifxmips_emulate)
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+ {
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+ val = ath_hal_eeprom(ah, reg, 0, 0);
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+ } else
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+#endif
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+ val = _OS_REG_READ(ah, reg);
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- val = _OS_REG_READ(ah, reg);
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#ifdef AH_DEBUG
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if (ath_hal_debug > 1)
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- ath_hal_printf(ah, "%s: READ 0x%x => 0x%x\n",
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+ ath_hal_printf(ah, "%s: READ 0x%x => 0x%x\n",
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(ath_hal_func ?: "unknown"), reg, val);
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#endif
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return val;
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@@ -581,7 +634,9 @@
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{
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const char *sep;
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int i;
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-
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+#ifdef CONFIG_IFXMIPS
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+ ifxmips_emulate = ifxmips_has_brn_block();
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+#endif
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printk(KERN_INFO "%s: %s (", dev_info, ath_hal_version);
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sep = "";
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for (i = 0; ath_hal_buildopts[i] != NULL; i++) {
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