ipq806x: reduce PCIe buffer size setting to fix potential data corruption issues

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47545

target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch

@@ -229,8 +229,8 @@
 +	writel(upper_32_bits(pp->mem_bus_addr),
 +	       pcie->dbi + PCIE20_PLR_IATU_UTAR);
 +
-+	/* 1K PCIE buffer setting */
-+	writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++	/* 256B PCIE buffer setting */
++	writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 +	writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 +}
 +

target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch

@@ -229,8 +229,8 @@
 +	writel(upper_32_bits(pp->mem_bus_addr),
 +	       pcie->dbi + PCIE20_PLR_IATU_UTAR);
 +
-+	/* 1K PCIE buffer setting */
-+	writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++	/* 256B PCIE buffer setting */
++	writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 +	writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 +}
 +