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@ -75,10 +75,10 @@ |
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#define AR71XX_CPU_IRQ_BASE 0 |
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#define AR71XX_MISC_IRQ_BASE 8 |
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#define AR71XX_MISC_IRQ_COUNT 8 |
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#define AR71XX_GPIO_IRQ_BASE 16 |
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#define AR71XX_MISC_IRQ_COUNT 32 |
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#define AR71XX_GPIO_IRQ_BASE 40 |
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#define AR71XX_GPIO_IRQ_COUNT 32 |
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#define AR71XX_PCI_IRQ_BASE 48 |
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#define AR71XX_PCI_IRQ_BASE 72 |
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#define AR71XX_PCI_IRQ_COUNT 8 |
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#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) |
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@ -96,6 +96,11 @@ |
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#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) |
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#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) |
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#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) |
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#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8) |
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#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9) |
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#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10) |
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#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11) |
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#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12) |
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#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) |
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@ -465,6 +470,12 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear); |
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#define AR91XX_DDR_REG_FLUSH_USB 0x84 |
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#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 |
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#define AR934X_DDR_REG_FLUSH_GE0 0x9c |
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#define AR934X_DDR_REG_FLUSH_GE1 0xa0 |
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#define AR934X_DDR_REG_FLUSH_USB 0xa4 |
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#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 |
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#define PCI_WIN0_OFFS 0x10000000 |
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#define PCI_WIN1_OFFS 0x11000000 |
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#define PCI_WIN2_OFFS 0x12000000 |
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@ -564,6 +575,11 @@ void ar71xx_ddr_flush(u32 reg); |
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#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ |
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#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ |
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#define MISC_INT_ENET_LINK BIT(12) |
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#define MISC_INT_DDR_PERF BIT(11) |
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#define MISC_INT_TIMER4 BIT(10) |
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#define MISC_INT_TIMER3 BIT(9) |
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#define MISC_INT_TIMER2 BIT(8) |
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#define MISC_INT_DMA BIT(7) |
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#define MISC_INT_OHCI BIT(6) |
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#define MISC_INT_PERFC BIT(5) |
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