ramips: Fix MT7621 pinmux bits for uart3, uart2, mdio

The MT7621 uses a 2 bit wide configuration of the sdhci, spi, mdio, pcie,
wdt, uart2 and uart3 in the GPIO_MODE register. It was correctly done
for sdhci, spi, pcie and wdt, The same has to be done for uart3, uart2
and mdio.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 46645

target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch

@@ -520,7 +520,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 --- /dev/null
 +++ b/arch/mips/ralink/mt7621.c
-@@ -0,0 +1,192 @@
+@@ -0,0 +1,209 @@
 +/*
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License version 2 as published
@@ -555,8 +555,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +#define MT7621_GPIO_MODE_UART1		1
 +#define MT7621_GPIO_MODE_I2C		2
-+#define MT7621_GPIO_MODE_UART3		3
-+#define MT7621_GPIO_MODE_UART2		5
++#define MT7621_GPIO_MODE_UART3_MASK	0x3
++#define MT7621_GPIO_MODE_UART3_SHIFT	3
++#define MT7621_GPIO_MODE_UART3_GPIO	1
++#define MT7621_GPIO_MODE_UART2_MASK	0x3
++#define MT7621_GPIO_MODE_UART2_SHIFT	5
++#define MT7621_GPIO_MODE_UART2_GPIO	1
 +#define MT7621_GPIO_MODE_JTAG		7
 +#define MT7621_GPIO_MODE_WDT_MASK	0x3
 +#define MT7621_GPIO_MODE_WDT_SHIFT	8
@@ -566,7 +570,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT7621_GPIO_MODE_PCIE_MASK	0x3
 +#define MT7621_GPIO_MODE_PCIE_SHIFT	10
 +#define MT7621_GPIO_MODE_PCIE_GPIO	1
-+#define MT7621_GPIO_MODE_MDIO		12
++#define MT7621_GPIO_MODE_MDIO_MASK	0x3
++#define MT7621_GPIO_MODE_MDIO_SHIFT	12
++#define MT7621_GPIO_MODE_MDIO_GPIO	1
 +#define MT7621_GPIO_MODE_RGMII1		14
 +#define MT7621_GPIO_MODE_RGMII2		15
 +#define MT7621_GPIO_MODE_SPI_MASK	0x3
@@ -578,8 +584,16 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart", 0, 1, 2) };
 +static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
-+static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
-+static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
++static struct rt2880_pmx_func uart3_grp[] = {
++	FUNC("uart", 0, 5, 4),
++	FUNC("i2s", 2, 5, 4),
++	FUNC("spdif", 3, 5, 4),
++};
++static struct rt2880_pmx_func uart2_grp[] = {
++	FUNC("uart", 0, 9, 4),
++	FUNC("pcm", 2, 9, 4),
++	FUNC("spdif", 3, 9, 4),
++};
 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
 +static struct rt2880_pmx_func wdt_grp[] = {
 +	FUNC("wdt rst", 0, 18, 1),
@@ -604,14 +618,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
 +	GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
 +	GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
-+	GRP("uart3", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
-+	GRP("uart2", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
++	GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
++		MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
++	GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
++		MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
 +	GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
 +	GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
 +		MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
 +	GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
 +		MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
-+	GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
++	GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
++		MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
 +	GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
 +	GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
 +		MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),