Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 35211master
parent
29c21b973b
commit
7e1e7063c2
@ -0,0 +1,28 @@ |
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The pcim_*() functions are used by the libata-sff subsystem, and this
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subsystem is used for many SATA drivers on ARM platforms that do not
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necessarily have I/O ports.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
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Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
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Cc: Yinghai Lu <yinghai@kernel.org>
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Cc: linux-kernel@vger.kernel.org
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---
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lib/devres.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/lib/devres.c
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+++ b/lib/devres.c
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@@ -195,6 +195,7 @@ void devm_ioport_unmap(struct device *de
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devm_ioport_map_match, (void *)addr));
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}
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EXPORT_SYMBOL(devm_ioport_unmap);
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+#endif /* CONFIG_HAS_IOPORT */
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#ifdef CONFIG_PCI
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/*
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@@ -400,4 +401,3 @@ void pcim_iounmap_regions(struct pci_dev
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}
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EXPORT_SYMBOL(pcim_iounmap_regions);
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#endif /* CONFIG_PCI */
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-#endif /* CONFIG_HAS_IOPORT */
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@ -0,0 +1,24 @@ |
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The Armada 370 has two gatable clocks for each PCIe interface, and we
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want both of them to be enabled. We therefore make one of the two
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clocks a child of the other, as we did for the sataX and sataXlnk
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clocks on Armada XP.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Cc: Mike Turquette <mturquette@linaro.org>
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---
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drivers/clk/mvebu/clk-gating-ctrl.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/clk/mvebu/clk-gating-ctrl.c
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+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
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@@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __in
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{ "pex1_en", NULL, 2 },
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{ "ge1", NULL, 3 },
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{ "ge0", NULL, 4 },
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- { "pex0", NULL, 5 },
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- { "pex1", NULL, 9 },
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+ { "pex0", "pex0_en", 5 },
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+ { "pex1", "pex1_en", 9 },
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{ "sata0", NULL, 15 },
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{ "sdio", NULL, 17 },
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{ "tdm", NULL, 25 },
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@ -0,0 +1,28 @@ |
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Instead of hardcoding "1" as being the bit value to enable an address
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decoding window, introduce and use a WIN_CTRL_ENABLE definition.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/plat-orion/addr-map.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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--- a/arch/arm/plat-orion/addr-map.c
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+++ b/arch/arm/plat-orion/addr-map.c
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@@ -38,6 +38,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
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* CPU Address Decode Windows registers
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*/
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#define WIN_CTRL_OFF 0x0000
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+#define WIN_CTRL_ENABLE BIT(0)
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#define WIN_BASE_OFF 0x0004
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_HI_OFF 0x000c
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@@ -79,7 +80,8 @@ void __init orion_setup_cpu_win(const st
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}
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base_high = base & 0xffff0000;
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- ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
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+ ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) |
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+ WIN_CTRL_ENABLE;
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writel(base_high, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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@ -0,0 +1,80 @@ |
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In the address decoding code, the orion_disable_wins() function is
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used at boot time to disable all address decoding windows, before
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configuring only the ones that are needed. This allows to make sure
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that no configuration is left from the bootloader.
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As a preparation for the introduction of address decoding window
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allocation/deallocation function, we refactor this function into an
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orion_disable_cpu_win() which disables a single window.
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The orion_config_wins() function is changed to call
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orion_disable_cpu_win() in a loop, to preserve an identical behavior.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/plat-orion/addr-map.c | 35 +++++++++++++++++------------------
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1 file changed, 17 insertions(+), 18 deletions(-)
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--- a/arch/arm/plat-orion/addr-map.c
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+++ b/arch/arm/plat-orion/addr-map.c
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@@ -95,6 +95,19 @@ void __init orion_setup_cpu_win(const st
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}
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}
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+static void __init orion_disable_cpu_win(const struct orion_addr_map_cfg *cfg,
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+ const int win)
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+{
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+ void __iomem *addr = cfg->win_cfg_base(cfg, win);
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+
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+ writel(0, addr + WIN_BASE_OFF);
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+ writel(0, addr + WIN_CTRL_OFF);
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+ if (cfg->cpu_win_can_remap(cfg, win)) {
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+ writel(0, addr + WIN_REMAP_LO_OFF);
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+ writel(0, addr + WIN_REMAP_HI_OFF);
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+ }
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+}
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+
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/*
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* Configure a number of windows.
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*/
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@@ -108,36 +121,22 @@ static void __init orion_setup_cpu_wins(
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}
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}
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-static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
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-{
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- void __iomem *addr;
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- int i;
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-
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- for (i = 0; i < cfg->num_wins; i++) {
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- addr = cfg->win_cfg_base(cfg, i);
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-
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- writel(0, addr + WIN_BASE_OFF);
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- writel(0, addr + WIN_CTRL_OFF);
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- if (cfg->cpu_win_can_remap(cfg, i)) {
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- writel(0, addr + WIN_REMAP_LO_OFF);
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- writel(0, addr + WIN_REMAP_HI_OFF);
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- }
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- }
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-}
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-
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/*
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* Disable, clear and configure windows.
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*/
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void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
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const struct orion_addr_map_info *info)
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{
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+ int win;
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+
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if (!cfg->cpu_win_can_remap)
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cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
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if (!cfg->win_cfg_base)
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cfg->win_cfg_base = orion_win_cfg_base;
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- orion_disable_wins(cfg);
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+ for (win = 0; win < cfg->num_wins; win++)
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+ orion_disable_cpu_win(cfg, win);
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if (info)
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orion_setup_cpu_wins(cfg, info);
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@ -0,0 +1,96 @@ |
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In the address decoding code, we implement two new functions:
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orion_alloc_cpu_win() and orion_free_cpu_win(). The first function
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finds an unused address decoding window, and configures it according
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to the given arguments (in terms of base address, size, target,
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attributes). The second function frees an address decoding window,
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given a physical base address.
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Those two new functions will be used by the PCIe code, which needs to
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dynamically register address decoding windows depending on the PCIe
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devices that are detected.
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The orion_free_cpu_win() function is only here to handle error cases
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in the PCIe devices initialization, in the normal case, address
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decoding windows are never freed.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/plat-orion/addr-map.c | 50 +++++++++++++++++++++++++++
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arch/arm/plat-orion/include/plat/addr-map.h | 7 ++++
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2 files changed, 57 insertions(+)
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--- a/arch/arm/plat-orion/addr-map.c
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+++ b/arch/arm/plat-orion/addr-map.c
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@@ -109,6 +109,56 @@ static void __init orion_disable_cpu_win
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}
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/*
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+ * Find an unused address decoding window, and enable it according to
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+ * the arguments passed (base, size, target, attributes, remap).
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+ */
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+int __init orion_alloc_cpu_win(const struct orion_addr_map_cfg *cfg,
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+ const u32 base, const u32 size,
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+ const u8 target, const u8 attr, const int remap)
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+{
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+ int win;
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+
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+ for (win = 0; win < cfg->num_wins; win++) {
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+ void __iomem *addr = cfg->win_cfg_base(cfg, win);
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+ u32 ctrl = readl(addr + WIN_CTRL_OFF);
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+ if (!(ctrl & WIN_CTRL_ENABLE))
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+ break;
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+ }
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+
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+ /* No more windows available */
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+ if (win == cfg->num_wins)
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+ return -ENOMEM;
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+
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+ orion_setup_cpu_win(cfg, win, base, size, target, attr, remap);
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+ return 0;
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+}
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+
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+/*
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+ * Free an address decoding window, given its base address.
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+ */
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+int __init orion_free_cpu_win(const struct orion_addr_map_cfg *cfg,
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+ const u32 base)
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+{
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+ int win;
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+
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+ for (win = 0; win < cfg->num_wins; win++) {
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+ void __iomem *addr = cfg->win_cfg_base(cfg, win);
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+ u32 winbase = readl(addr + WIN_BASE_OFF);
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+ u32 ctrl = readl(addr + WIN_CTRL_OFF);
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+
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+ if (!(ctrl & WIN_CTRL_ENABLE))
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+ continue;
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+
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+ if (winbase == (base & 0xffff0000)) {
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+ orion_disable_cpu_win(cfg, win);
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+ return 0;
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+ }
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+/*
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* Configure a number of windows.
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*/
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static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
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--- a/arch/arm/plat-orion/include/plat/addr-map.h
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+++ b/arch/arm/plat-orion/include/plat/addr-map.h
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@@ -49,6 +49,13 @@ void __init orion_setup_cpu_win(const st
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const u32 size, const u8 target,
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const u8 attr, const int remap);
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+int __init orion_alloc_cpu_win(const struct orion_addr_map_cfg *cfg,
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+ const u32 base, const u32 size,
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+ const u8 target, const u8 attr, const int remap);
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+
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+int __init orion_free_cpu_win(const struct orion_addr_map_cfg *cfg,
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+ const u32 base);
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+
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void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
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const void __iomem *ddr_window_cpu_base);
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#endif
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@ -0,0 +1,201 @@ |
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This commit adds two functions armada_370_xp_alloc_pcie_window() and
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armada_370_xp_free_pcie_window() that respectively allocate and free
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an address decoding window pointing to either a memory or I/O region
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of a PCIe device.
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Those functions will be used by the PCIe driver to create and remove
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those regions depending on the PCIe devices that are detected.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/mach-mvebu/addr-map.c | 156 ++++++++++++++++++++++++++++++++++++++--
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arch/arm/mach-mvebu/common.h | 4 ++
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2 files changed, 156 insertions(+), 4 deletions(-)
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--- a/arch/arm/mach-mvebu/addr-map.c
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+++ b/arch/arm/mach-mvebu/addr-map.c
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@@ -24,14 +24,10 @@
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#define ARMADA_XP_TARGET_DEV_BUS 1
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#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
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#define ARMADA_XP_TARGET_ETH1 3
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-#define ARMADA_XP_TARGET_PCIE_0_2 4
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#define ARMADA_XP_TARGET_ETH0 7
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-#define ARMADA_XP_TARGET_PCIE_1_3 8
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#define ARMADA_370_TARGET_DEV_BUS 1
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#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
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-#define ARMADA_370_TARGET_PCIE_0 4
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-#define ARMADA_370_TARGET_PCIE_1 8
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#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
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#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
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@@ -89,6 +85,158 @@ static struct __initdata orion_addr_map_
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.win_cfg_base = armada_cfg_base,
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};
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+#ifdef CONFIG_PCI
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+/*
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+ * PCIe windows allocation code.
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+ */
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+#define ARMADA_370_XP_PCIE_MEM_START 0xC0000000
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+#define ARMADA_370_XP_PCIE_MEM_END (ARMADA_370_XP_PCIE_MEM_START + SZ_256M)
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+#define ARMADA_370_XP_PCIE_IO_START 0xF2000000
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+#define ARMADA_370_XP_PCIE_IO_END (ARMADA_370_XP_PCIE_IO_START + SZ_1M)
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+
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+static unsigned long armada_370_xp_pcie_memaddr = ARMADA_370_XP_PCIE_MEM_START;
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+static unsigned long armada_370_xp_pcie_ioaddr = ARMADA_370_XP_PCIE_IO_START;
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+
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+/*
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+ * This structure and the following arrays allow to map a PCIe (port,
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+ * lane) tuple to the corresponding (target, attribute) tuple needed
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+ * to configure an address decoding window for the given PCIe (port,
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+ * lane).
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+ */
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+struct pcie_mapping {
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+ int port;
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+ int lane;
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+ u8 target;
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+ u8 attr;
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+};
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+
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+struct pcie_mapping armada_xp_pcie_mappings[] = {
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+ { .port = 0, .lane = 0, .target = 4, .attr = 0xE0 },
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+ { .port = 0, .lane = 1, .target = 4, .attr = 0xD0 },
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+ { .port = 0, .lane = 2, .target = 4, .attr = 0xB0 },
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+ { .port = 0, .lane = 3, .target = 4, .attr = 0x70 },
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+ { .port = 1, .lane = 0, .target = 8, .attr = 0xE0 },
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+ { .port = 1, .lane = 1, .target = 8, .attr = 0xD0 },
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+ { .port = 1, .lane = 2, .target = 8, .attr = 0xB0 },
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+ { .port = 1, .lane = 3, .target = 8, .attr = 0x70 },
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+ { .port = 2, .lane = 0, .target = 4, .attr = 0xF0 },
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+ { .port = 3, .lane = 0, .target = 8, .attr = 0xF0 },
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+ { .port = -1 },
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+};
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+
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+struct pcie_mapping armada_370_pcie_mappings[] = {
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+ { .port = 0, .lane = 0, .target = 4, .attr = 0xE0 },
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+ { .port = 1, .lane = 0, .target = 8, .attr = 0xE0 },
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+ { .port = -1 },
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+};
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+
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+/*
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+ * This function finds an available physical address range between
|
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+ * ARMADA_370_XP_PCIE_MEM_START and ARMADA_370_XP_PCIE_MEM_END (for
|
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+ * PCIe memory regions) or between ARMADA_370_XP_PCIE_IO_START and
|
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+ * ARMADA_370_XP_PCIE_IO_END (for PCIe I/O regions) and creates an
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+ * address decoding window from this allocated address pointing to the
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+ * right PCIe device.
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+ *
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+ * An error code is returned, the allocated base address is returned
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+ * through the 'outbase' argument.
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+ */
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+int __init armada_370_xp_alloc_pcie_window(int pcie_port, int pcie_lane,
|
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+ int type, u32 size,
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+ unsigned long *outbase)
|
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+{
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+ struct pcie_mapping *mapping, *mappings;
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+ u8 target, attr;
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+ u32 base;
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+ int ret;
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+
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+ if (of_machine_is_compatible("marvell,armadaxp"))
|
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+ mappings = armada_xp_pcie_mappings;
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+ else if (of_machine_is_compatible("marvell,armada370"))
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+ mappings = armada_370_pcie_mappings;
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+ else
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+ return -ENODEV;
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+
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+ for (mapping = mappings; mapping->port != -1; mapping++)
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+ if (mapping->port == pcie_port && mapping->lane == pcie_lane)
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+ break;
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+
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+ if (mapping->port == -1)
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+ return -ENODEV;
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+
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+ target = mapping->target;
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+ attr = mapping->attr;
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+
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+ if (type == IORESOURCE_MEM) {
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+ /*
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+ * Bit 3 of the attributes indicates that it is a
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+ * memory region, as opposed to an I/O region
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+ */
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+ attr |= (1 << 3);
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+
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+ if (armada_370_xp_pcie_memaddr + size >
|
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+ ARMADA_370_XP_PCIE_MEM_END)
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+ return -ENOMEM;
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+
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+ base = armada_370_xp_pcie_memaddr;
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+ armada_370_xp_pcie_memaddr += size;
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+
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+ ret = orion_alloc_cpu_win(&addr_map_cfg, base, size, target,
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+ attr, -1);
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+ if (ret) {
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+ armada_370_xp_pcie_memaddr -= size;
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+ return ret;
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+ }
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+ } else if (type == IORESOURCE_IO) {
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+ if (armada_370_xp_pcie_ioaddr + size >
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+ ARMADA_370_XP_PCIE_IO_END)
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+ return -ENOMEM;
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+
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+ base = armada_370_xp_pcie_ioaddr;
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+ armada_370_xp_pcie_ioaddr += size;
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+
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+ ret = orion_alloc_cpu_win(&addr_map_cfg, base, size, target,
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+ attr, -1);
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+ if (ret) {
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+ armada_370_xp_pcie_ioaddr -= size;
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+ return ret;
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||||
+ }
|
||||
+ } else
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ *outbase = base;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Frees an address decoding window previously allocated by
|
||||
+ * armada_370_xp_alloc_pcie_window(). Note that only the last window
|
||||
+ * allocated for a given type (MEM or IO) can be freed, due to the
|
||||
+ * simplicity of the allocator. This is however sufficient to handle
|
||||
+ * the error cases when initializing one PCIe device.
|
||||
+ */
|
||||
+int __init armada_370_xp_free_pcie_window(int type, unsigned long base,
|
||||
+ u32 size)
|
||||
+{
|
||||
+ if (type == IORESOURCE_MEM) {
|
||||
+ /* We can only free the last allocated window */
|
||||
+ if (base + size != armada_370_xp_pcie_memaddr)
|
||||
+ return -EINVAL;
|
||||
+ orion_free_cpu_win(&addr_map_cfg, base);
|
||||
+ armada_370_xp_pcie_memaddr -= size;
|
||||
+ } else if (type == IORESOURCE_IO) {
|
||||
+ /* We can only free the last allocated window */
|
||||
+ if (base + size != armada_370_xp_pcie_ioaddr)
|
||||
+ return -EINVAL;
|
||||
+ orion_free_cpu_win(&addr_map_cfg, base);
|
||||
+ armada_370_xp_pcie_ioaddr -= size;
|
||||
+ } else
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
static int __init armada_setup_cpu_mbus(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
--- a/arch/arm/mach-mvebu/common.h
|
||||
+++ b/arch/arm/mach-mvebu/common.h
|
||||
@@ -25,4 +25,8 @@ int armada_370_xp_coherency_init(void);
|
||||
int armada_370_xp_pmsu_init(void);
|
||||
void armada_xp_secondary_startup(void);
|
||||
extern struct smp_operations armada_xp_smp_ops;
|
||||
+
|
||||
+int armada_370_xp_alloc_pcie_window(int pcie_port, int pcie_lane,
|
||||
+ int type, u32 size, unsigned long *outbase);
|
||||
+int armada_370_xp_free_pcie_window(int type, unsigned long base, u32 size);
|
||||
#endif
|
@ -0,0 +1,25 @@ |
||||
mvebu is a new-style Orion platform, so it only selects PLAT_ORION,
|
||||
but not PLAT_ORION_LEGACY. It will however need the common PCIe code
|
||||
from plat-orion, so make this code available for PLAT_ORION platforms
|
||||
as a whole, and not only PLAT_ORION_LEGACY platforms.
|
||||
|
||||
We also take this opportunity to build the PCIe code only when
|
||||
CONFIG_PCI is enabled.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/plat-orion/Makefile | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/plat-orion/Makefile
|
||||
+++ b/arch/arm/plat-orion/Makefile
|
||||
@@ -4,7 +4,8 @@
|
||||
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
|
||||
obj-y += addr-map.o
|
||||
+obj-$(CONFIG_PCI) += pcie.o
|
||||
|
||||
orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
|
||||
-obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
|
||||
+obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o time.o common.o mpp.o
|
||||
obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
|
@ -0,0 +1,474 @@ |
||||
This driver implements the hw_pci operations needed by the core ARM
|
||||
PCI code to setup PCI devices and get their corresponding IRQs, and
|
||||
the pci_ops operations that are used by the PCI core to read/write the
|
||||
configuration space of PCI devices.
|
||||
|
||||
In addition, this driver enumerates the different PCIe slots, and for
|
||||
those having a device plugged in, it allocates the necessary address
|
||||
decoding windows, using the new armada_370_xp_alloc_pcie_window()
|
||||
function from mach-mvebu/addr-map.c.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
.../devicetree/bindings/pci/armada-370-xp-pcie.txt | 136 +++++++++
|
||||
arch/arm/mach-mvebu/Makefile | 1 +
|
||||
arch/arm/mach-mvebu/pcie.c | 306 ++++++++++++++++++++
|
||||
3 files changed, 443 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/pci/armada-370-xp-pcie.txt
|
||||
create mode 100644 arch/arm/mach-mvebu/pcie.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/pci/armada-370-xp-pcie.txt
|
||||
@@ -0,0 +1,136 @@
|
||||
+* Marvell Armada 370/XP PCIe interfaces
|
||||
+
|
||||
+Mandatory properties:
|
||||
+- compatible: must be "marvell,armada-370-xp-pcie"
|
||||
+- status: either "disabled" or "okay"
|
||||
+- #address-cells, set to <1>
|
||||
+- #size-cells, set to <1>
|
||||
+- ranges: describes the association between the physical addresses of
|
||||
+ the PCIe registers for each PCIe interface with "virtual" addresses
|
||||
+ as seen by the sub-nodes. One entry per PCIe interface. Each entry
|
||||
+ must have 3 values: the "virtual" address seen by the sub-nodes, the
|
||||
+ real physical address of the PCIe registers, and the size.
|
||||
+
|
||||
+In addition, the Device Tree node must have sub-nodes describing each
|
||||
+PCIe interface, having the following mandatory properties:
|
||||
+- reg: the address and size of the PCIe registers (translated
|
||||
+ addresses according to the ranges property of the parent)
|
||||
+- interrupts: the interrupt number of this PCIe interface
|
||||
+- clocks: the clock associated to this PCIe interface
|
||||
+- marvell,pcie-port: the physical PCIe port number
|
||||
+- status: either "disabled" or "okay"
|
||||
+
|
||||
+and the following optional properties:
|
||||
+- marvell,pcie-lane: the physical PCIe lane number, for ports having
|
||||
+ multiple lanes. If this property is not found, we assume that the
|
||||
+ value is 0.
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+pcie-controller {
|
||||
+ compatible = "marvell,armada-370-xp-pcie";
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
|
||||
+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
|
||||
+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
|
||||
+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
|
||||
+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
|
||||
+ 0x10000 0xd0080000 0x2000 /* port1x1_port0 */
|
||||
+ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */
|
||||
+ 0x14000 0xd0084000 0x2000 /* port1x1_port1 */
|
||||
+ 0x18000 0xd0088000 0x2000 /* port1x1_port2 */
|
||||
+ 0x1C000 0xd008C000 0x2000 /* port1x1_port3 */>;
|
||||
+
|
||||
+ pcie0.0@0xd0040000 {
|
||||
+ reg = <0x0 0x2000>;
|
||||
+ interrupts = <58>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.1@0xd0044000 {
|
||||
+ reg = <0x4000 0x2000>;
|
||||
+ interrupts = <59>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.2@0xd0048000 {
|
||||
+ reg = <0x8000 0x2000>;
|
||||
+ interrupts = <60>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.3@0xd004C000 {
|
||||
+ reg = <0xC000 0x2000>;
|
||||
+ interrupts = <61>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.0@0xd0040000 {
|
||||
+ reg = <0x10000 0x2000>;
|
||||
+ interrupts = <62>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.1@0xd0044000 {
|
||||
+ reg = <0x14000 0x2000>;
|
||||
+ interrupts = <63>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.2@0xd0048000 {
|
||||
+ reg = <0x18000 0x2000>;
|
||||
+ interrupts = <64>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.3@0xd004C000 {
|
||||
+ reg = <0x1C000 0x2000>;
|
||||
+ interrupts = <65>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie2@0xd0042000 {
|
||||
+ reg = <0x2000 0x2000>;
|
||||
+ interrupts = <99>;
|
||||
+ clocks = <&gateclk 7>;
|
||||
+ marvell,pcie-port = <2>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie3@0xd0082000 {
|
||||
+ reg = <0x12000 0x2000>;
|
||||
+ interrupts = <103>;
|
||||
+ clocks = <&gateclk 8>;
|
||||
+ marvell,pcie-port = <3>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
--- a/arch/arm/mach-mvebu/Makefile
|
||||
+++ b/arch/arm/mach-mvebu/Makefile
|
||||
@@ -5,3 +5,4 @@ obj-y += system-controller.o
|
||||
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
+obj-$(CONFIG_PCI) += pcie.o
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/mach-mvebu/pcie.c
|
||||
@@ -0,0 +1,306 @@
|
||||
+/*
|
||||
+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/of_pci.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <plat/pcie.h>
|
||||
+#include "common.h"
|
||||
+
|
||||
+struct pcie_port {
|
||||
+ u8 root_bus_nr;
|
||||
+ void __iomem *base;
|
||||
+ spinlock_t conf_lock;
|
||||
+ int irq;
|
||||
+ struct resource res;
|
||||
+ int haslink;
|
||||
+ u32 port;
|
||||
+ u32 lane;
|
||||
+ struct clk *clk;
|
||||
+};
|
||||
+
|
||||
+static struct pcie_port *pcie_ports;
|
||||
+
|
||||
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
|
||||
+{
|
||||
+ /*
|
||||
+ * Don't go out when trying to access --
|
||||
+ * 1. nonexisting device on local bus
|
||||
+ * 2. where there's no device connected (no link)
|
||||
+ */
|
||||
+ if (bus == pp->root_bus_nr && dev == 0)
|
||||
+ return 1;
|
||||
+
|
||||
+ if (!orion_pcie_link_up(pp->base))
|
||||
+ return 0;
|
||||
+
|
||||
+ if (bus == pp->root_bus_nr && dev != 1)
|
||||
+ return 0;
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
|
||||
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
|
||||
+ * transactions are atomic.
|
||||
+ */
|
||||
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
||||
+ int size, u32 *val)
|
||||
+{
|
||||
+ struct pci_sys_data *sys = bus->sysdata;
|
||||
+ struct pcie_port *pp = sys->private_data;
|
||||
+ unsigned long flags;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
|
||||
+ *val = 0xffffffff;
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+ }
|
||||
+
|
||||
+ spin_lock_irqsave(&pp->conf_lock, flags);
|
||||
+ ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
|
||||
+ spin_unlock_irqrestore(&pp->conf_lock, flags);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ struct pci_sys_data *sys = bus->sysdata;
|
||||
+ struct pcie_port *pp = sys->private_data;
|
||||
+ unsigned long flags;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ spin_lock_irqsave(&pp->conf_lock, flags);
|
||||
+ ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
|
||||
+ spin_unlock_irqrestore(&pp->conf_lock, flags);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops pcie_ops = {
|
||||
+ .read = pcie_rd_conf,
|
||||
+ .write = pcie_wr_conf,
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * Returns 0 when the device could not be initialized, 1 when
|
||||
+ * initialization is successful
|
||||
+ */
|
||||
+static int __init armada_370_xp_pcie_setup(int nr, struct pci_sys_data *sys)
|
||||
+{
|
||||
+ struct pcie_port *port = &pcie_ports[nr];
|
||||
+ unsigned long membase, iobase;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!port->haslink)
|
||||
+ return 0;
|
||||
+
|
||||
+ sys->private_data = port;
|
||||
+ port->root_bus_nr = sys->busnr;
|
||||
+ spin_lock_init(&port->conf_lock);
|
||||
+
|
||||
+ ret = armada_370_xp_alloc_pcie_window(port->port, port->lane,
|
||||
+ IORESOURCE_MEM, SZ_64M, &membase);
|
||||
+ if (ret) {
|
||||
+ pr_err("PCIe%d.%d: Cannot get memory window, device disabled\n",
|
||||
+ port->port, port->lane);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ ret = armada_370_xp_alloc_pcie_window(port->port, port->lane,
|
||||
+ IORESOURCE_IO, SZ_64K, &iobase);
|
||||
+ if (ret) {
|
||||
+ pr_err("PCIe%d.%d: Cannot get I/O window, device disabled\n",
|
||||
+ port->port, port->lane);
|
||||
+ armada_370_xp_free_pcie_window(IORESOURCE_MEM, membase, SZ_64M);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ port->res.name = kasprintf(GFP_KERNEL, "PCIe %d.%d MEM",
|
||||
+ port->port, port->lane);
|
||||
+ if (!port->res.name) {
|
||||
+ armada_370_xp_free_pcie_window(IORESOURCE_IO, iobase, SZ_64K);
|
||||
+ armada_370_xp_free_pcie_window(IORESOURCE_MEM, membase, SZ_64M);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ port->res.start = membase;
|
||||
+ port->res.end = membase + SZ_32M - 1;
|
||||
+ port->res.flags = IORESOURCE_MEM;
|
||||
+
|
||||
+ pci_ioremap_io(SZ_64K * sys->busnr, iobase);
|
||||
+
|
||||
+ if (request_resource(&iomem_resource, &port->res)) {
|
||||
+ pr_err("PCIe%d.%d: Cannot request memory resource\n",
|
||||
+ port->port, port->lane);
|
||||
+ kfree(port->res.name);
|
||||
+ armada_370_xp_free_pcie_window(IORESOURCE_IO, iobase, SZ_64K);
|
||||
+ armada_370_xp_free_pcie_window(IORESOURCE_MEM, membase, SZ_64M);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ pci_add_resource_offset(&sys->resources, &port->res, sys->mem_offset);
|
||||
+
|
||||
+ orion_pcie_set_local_bus_nr(port->base, sys->busnr);
|
||||
+ orion_pcie_setup(port->base);
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
|
||||
+{
|
||||
+ /*
|
||||
+ * Prevent enumeration of root complex.
|
||||
+ */
|
||||
+ if (dev->bus->parent == NULL && dev->devfn == 0) {
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
+ dev->resource[i].start = 0;
|
||||
+ dev->resource[i].end = 0;
|
||||
+ dev->resource[i].flags = 0;
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
|
||||
+
|
||||
+static int __init armada_370_xp_pcie_map_irq(const struct pci_dev *dev, u8 slot,
|
||||
+ u8 pin)
|
||||
+{
|
||||
+ struct pci_sys_data *sys = dev->sysdata;
|
||||
+ struct pcie_port *port = sys->private_data;
|
||||
+
|
||||
+ return port->irq;
|
||||
+}
|
||||
+
|
||||
+static struct hw_pci armada_370_xp_pci __initdata = {
|
||||
+ .setup = armada_370_xp_pcie_setup,
|
||||
+ .map_irq = armada_370_xp_pcie_map_irq,
|
||||
+ .ops = &pcie_ops,
|
||||
+};
|
||||
+
|
||||
+static int __init armada_370_xp_pcie_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *child;
|
||||
+ int nports, i;
|
||||
+
|
||||
+ nports = 0;
|
||||
+ for_each_child_of_node(pdev->dev.of_node, child) {
|
||||
+ if (!of_device_is_available(child))
|
||||
+ continue;
|
||||
+ nports++;
|
||||
+ }
|
||||
+
|
||||
+ pcie_ports = devm_kzalloc(&pdev->dev, nports * sizeof(*pcie_ports),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!pcie_ports)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ i = 0;
|
||||
+ for_each_child_of_node(pdev->dev.of_node, child) {
|
||||
+ struct pcie_port *port = &pcie_ports[i];
|
||||
+
|
||||
+ if (!of_device_is_available(child))
|
||||
+ continue;
|
||||
+
|
||||
+ if (of_property_read_u32(child, "marvell,pcie-port",
|
||||
+ &port->port))
|
||||
+ continue;
|
||||
+
|
||||
+ if (of_property_read_u32(child, "marvell,pcie-lane",
|
||||
+ &port->lane))
|
||||
+ port->lane = 0;
|
||||
+
|
||||
+ port->base = of_iomap(child, 0);
|
||||
+ if (!port->base) {
|
||||
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
|
||||
+ port->port, port->lane);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ if (orion_pcie_link_up(port->base)) {
|
||||
+ port->haslink = 1;
|
||||
+ dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
|
||||
+ port->port, port->lane);
|
||||
+ } else {
|
||||
+ port->haslink = 0;
|
||||
+ dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
|
||||
+ port->port, port->lane);
|
||||
+ iounmap(port->base);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ port->irq = irq_of_parse_and_map(child, 0);
|
||||
+ if (port->irq == 0) {
|
||||
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot parse and map IRQ\n",
|
||||
+ port->port, port->lane);
|
||||
+ iounmap(port->base);
|
||||
+ port->haslink = 0;
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ port->clk = of_clk_get_by_name(child, NULL);
|
||||
+ if (!port->clk) {
|
||||
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
|
||||
+ port->port, port->lane);
|
||||
+ irq_dispose_mapping(port->irq);
|
||||
+ iounmap(port->base);
|
||||
+ port->haslink = 0;
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ clk_prepare_enable(port->clk);
|
||||
+
|
||||
+ i++;
|
||||
+ }
|
||||
+
|
||||
+ armada_370_xp_pci.nr_controllers = nports;
|
||||
+ pci_common_init(&armada_370_xp_pci);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id armada_370_xp_pcie_of_match_table[] = {
|
||||
+ { .compatible = "marvell,armada-370-xp-pcie", },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, armada_370_xp_pcie_of_match_table);
|
||||
+
|
||||
+static struct platform_driver armada_370_xp_pcie_driver = {
|
||||
+ .driver = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .name = "armada-370-xp-pcie",
|
||||
+ .of_match_table =
|
||||
+ of_match_ptr(armada_370_xp_pcie_of_match_table),
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int armada_370_xp_pcie_init(void)
|
||||
+{
|
||||
+ return platform_driver_probe(&armada_370_xp_pcie_driver,
|
||||
+ armada_370_xp_pcie_probe);
|
||||
+}
|
||||
+
|
||||
+subsys_initcall(armada_370_xp_pcie_init);
|
||||
+
|
||||
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
|
||||
+MODULE_DESCRIPTION("Marvell Armada 370/XP PCIe driver");
|
||||
+MODULE_LICENSE("GPL");
|
@ -0,0 +1,20 @@ |
||||
Now that the PCIe driver for mvebu has been integrated and all its
|
||||
relevant dependencies, we can mark the ARCH_MVEBU platform has
|
||||
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/mach-mvebu/Kconfig | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm/mach-mvebu/Kconfig
|
||||
+++ b/arch/arm/mach-mvebu/Kconfig
|
||||
@@ -13,6 +13,8 @@ config ARCH_MVEBU
|
||||
select MVEBU_CLK_CORE
|
||||
select MVEBU_CLK_CPU
|
||||
select MVEBU_CLK_GATING
|
||||
+ select MIGHT_HAVE_PCI
|
||||
+ select PCI_QUIRKS if PCI
|
||||
|
||||
if ARCH_MVEBU
|
||||
|
@ -0,0 +1,40 @@ |
||||
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
|
||||
necessary Device Tree informations to make these interfaces availabel.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-370.dtsi | 25 +++++++++++++++++++++++++
|
||||
1 file changed, 25 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-370.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-370.dtsi
|
||||
@@ -153,5 +153,29 @@
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
+ pcie-controller {
|
||||
+ compatible = "marvell,armada-370-xp-pcie";
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0xd0040000 0x2000
|
||||
+ 0x2000 0xd0080000 0x2000>;
|
||||
+
|
||||
+ pcie0@0xd0040000 {
|
||||
+ reg = <0x0 0x2000>;
|
||||
+ interrupts = <58>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ status = "disabled";
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ };
|
||||
+
|
||||
+ pcie1@0xd0080000 {
|
||||
+ reg = <0x2000 0x2000>;
|
||||
+ interrupts = <62>;
|
||||
+ clocks = <&gateclk 9>;
|
||||
+ status = "disabled";
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
@ -0,0 +1,284 @@ |
||||
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
|
||||
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
|
||||
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
|
||||
units (two 4x or quad 1x and two 4x/1x). We therefore add the
|
||||
necessary Device Tree informations to make those PCIe interfaces
|
||||
usable.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 62 +++++++++++++++++
|
||||
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 72 +++++++++++++++++++
|
||||
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 112 ++++++++++++++++++++++++++++++
|
||||
3 files changed, 246 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
|
||||
@@ -76,5 +76,67 @@
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>;
|
||||
};
|
||||
+
|
||||
+ /*
|
||||
+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
+ * configured as x4 or quad x1 lanes. One unit is
|
||||
+ * x4/x1.
|
||||
+ */
|
||||
+ pcie-controller {
|
||||
+ compatible = "marvell,armada-370-xp-pcie";
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
|
||||
+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
|
||||
+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
|
||||
+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
|
||||
+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */>;
|
||||
+
|
||||
+ pcie0.0@0xd0040000 {
|
||||
+ reg = <0x0 0x2000>;
|
||||
+ interrupts = <58>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.1@0xd0044000 {
|
||||
+ reg = <0x4000 0x2000>;
|
||||
+ interrupts = <59>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.2@0xd0048000 {
|
||||
+ reg = <0x8000 0x2000>;
|
||||
+ interrupts = <60>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.3@0xd004C000 {
|
||||
+ reg = <0xC000 0x2000>;
|
||||
+ interrupts = <61>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie2@0xd0042000 {
|
||||
+ reg = <0x2000 0x2000>;
|
||||
+ interrupts = <99>;
|
||||
+ clocks = <&gateclk 7>;
|
||||
+ marvell,pcie-port = <2>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
|
||||
@@ -96,5 +96,77 @@
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ /*
|
||||
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
+ * configured as x4 or quad x1 lanes. One unit is
|
||||
+ * x4/x1.
|
||||
+ */
|
||||
+ pcie-controller {
|
||||
+ compatible = "marvell,armada-370-xp-pcie";
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
|
||||
+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
|
||||
+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
|
||||
+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
|
||||
+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
|
||||
+ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */>;
|
||||
+
|
||||
+ pcie0.0@0xd0040000 {
|
||||
+ reg = <0x0 0x2000>;
|
||||
+ interrupts = <58>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.1@0xd0044000 {
|
||||
+ reg = <0x4000 0x2000>;
|
||||
+ interrupts = <59>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.2@0xd0048000 {
|
||||
+ reg = <0x8000 0x2000>;
|
||||
+ interrupts = <60>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.3@0xd004C000 {
|
||||
+ reg = <0xC000 0x2000>;
|
||||
+ interrupts = <61>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie2@0xd0042000 {
|
||||
+ reg = <0x2000 0x2000>;
|
||||
+ interrupts = <99>;
|
||||
+ clocks = <&gateclk 7>;
|
||||
+ marvell,pcie-port = <2>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie3@0xd0082000 {
|
||||
+ reg = <0x12000 0x2000>;
|
||||
+ interrupts = <103>;
|
||||
+ clocks = <&gateclk 8>;
|
||||
+ marvell,pcie-port = <3>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
|
||||
@@ -111,5 +111,117 @@
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ /*
|
||||
+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
+ * configured as x4 or quad x1 lanes. Two units are
|
||||
+ * x4/x1.
|
||||
+ */
|
||||
+ pcie-controller {
|
||||
+ compatible = "marvell,armada-370-xp-pcie";
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
|
||||
+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
|
||||
+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
|
||||
+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
|
||||
+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
|
||||
+ 0x10000 0xd0080000 0x2000 /* port1x1_port0 */
|
||||
+ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */
|
||||
+ 0x14000 0xd0084000 0x2000 /* port1x1_port1 */
|
||||
+ 0x18000 0xd0088000 0x2000 /* port1x1_port2 */
|
||||
+ 0x1C000 0xd008C000 0x2000 /* port1x1_port3 */>;
|
||||
+
|
||||
+ pcie0.0@0xd0040000 {
|
||||
+ reg = <0x0 0x2000>;
|
||||
+ interrupts = <58>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.1@0xd0044000 {
|
||||
+ reg = <0x4000 0x2000>;
|
||||
+ interrupts = <59>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.2@0xd0048000 {
|
||||
+ reg = <0x8000 0x2000>;
|
||||
+ interrupts = <60>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie0.3@0xd004C000 {
|
||||
+ reg = <0xC000 0x2000>;
|
||||
+ interrupts = <61>;
|
||||
+ clocks = <&gateclk 5>;
|
||||
+ marvell,pcie-port = <0>;
|
||||
+ marvell,pcie-lane = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.0@0xd0040000 {
|
||||
+ reg = <0x10000 0x2000>;
|
||||
+ interrupts = <62>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.1@0xd0044000 {
|
||||
+ reg = <0x14000 0x2000>;
|
||||
+ interrupts = <63>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.2@0xd0048000 {
|
||||
+ reg = <0x18000 0x2000>;
|
||||
+ interrupts = <64>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1.3@0xd004C000 {
|
||||
+ reg = <0x1C000 0x2000>;
|
||||
+ interrupts = <65>;
|
||||
+ clocks = <&gateclk 6>;
|
||||
+ marvell,pcie-port = <1>;
|
||||
+ marvell,pcie-lane = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie2@0xd0042000 {
|
||||
+ reg = <0x2000 0x2000>;
|
||||
+ interrupts = <99>;
|
||||
+ clocks = <&gateclk 7>;
|
||||
+ marvell,pcie-port = <2>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie3@0xd0082000 {
|
||||
+ reg = <0x12000 0x2000>;
|
||||
+ interrupts = <103>;
|
||||
+ clocks = <&gateclk 8>;
|
||||
+ marvell,pcie-port = <3>;
|
||||
+ marvell,pcie-lane = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
@ -0,0 +1,24 @@ |
||||
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
|
||||
be used to plug mini-PCIe devices. We therefore enable the PCIe
|
||||
interface that corresponds to this slot.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
|
||||
@@ -130,5 +130,12 @@
|
||||
usb@d0052000 {
|
||||
status = "okay";
|
||||
};
|
||||
+ pcie-controller {
|
||||
+ status = "okay";
|
||||
+ /* Internal mini-PCIe connector */
|
||||
+ pcie0.0@0xd0040000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
@ -0,0 +1,44 @@ |
||||
The Marvell evaluation board (DB) for the Armada XP SoC has 6
|
||||
physicals full-size PCIe slots, so we enable the corresponding PCIe
|
||||
interfaces in the Device Tree.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-xp-db.dts | 27 +++++++++++++++++++++++++++
|
||||
1 file changed, 27 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-xp-db.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-db.dts
|
||||
@@ -109,5 +109,32 @@
|
||||
usb@d0052000 {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+ pcie-controller {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ /*
|
||||
+ * All 6 slots are physically present as
|
||||
+ * standard PCIe slots on the board.
|
||||
+ */
|
||||
+ pcie0.0@0xd0040000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ pcie0.1@0xd0044000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ pcie0.2@0xd0048000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ pcie0.3@0xd004C000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ pcie2@0xd0042000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ pcie3@0xd0082000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
@ -0,0 +1,32 @@ |
||||
The Globalscale Mirabox platform uses one PCIe interface for an
|
||||
available mini-PCIe slot, and the other PCIe interface for an internal
|
||||
USB 3.0 controller. We add the necessary Device Tree informations to
|
||||
enable those two interfaces.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-370-mirabox.dts | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
|
||||
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
|
||||
@@ -70,5 +70,19 @@
|
||||
usb@d0051000 {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+ pcie-controller {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ /* Internal mini-PCIe connector */
|
||||
+ pcie0@0xd0040000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
|
||||
+ pcie1@0xd0080000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
@ -0,0 +1,32 @@ |
||||
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
|
||||
physical full-size PCIe slots, so we enable the corresponding PCIe
|
||||
interfaces in the Device Tree.
|
||||
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-370-db.dts | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-370-db.dts
|
||||
+++ b/arch/arm/boot/dts/armada-370-db.dts
|
||||
@@ -82,5 +82,20 @@
|
||||
usb@d0051000 {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+ pcie-controller {
|
||||
+ status = "okay";
|
||||
+ /*
|
||||
+ * The two PCIe units are accessible through
|
||||
+ * both standard PCIe slots and mini-PCIe
|
||||
+ * slots on the board.
|
||||
+ */
|
||||
+ pcie0@0xd0040000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ pcie1@0xd0080000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
Loading…
Reference in new issue