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@ -41,7 +41,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev,
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const char *name, u32 addr,
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const void *data,
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@@ -338,6 +344,216 @@ err_unregister_ohci_dev:
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@@ -338,6 +344,165 @@ err_unregister_ohci_dev:
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return err;
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}
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@ -98,9 +98,8 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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+ iowrite32(0x0000009a, ccb->mii + 0x000);
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+ udelay(2);
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+
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+ switch (chipinfo->id) {
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+ case BCMA_CHIP_ID_BCM4707:
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+ if (chipinfo->rev == 4) {
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+ if (chipinfo->id == BCMA_CHIP_ID_BCM53018 ||
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+ chipinfo->id == BCMA_CHIP_ID_BCM4707 && chipinfo->rev == 4) {
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+ /* For NS-B0, USB3 PLL Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8000, ccb->mii + 0x004);
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@ -121,32 +120,39 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582e8000, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+
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+ /* Deasserting USB3 system reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+
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+ /* Set ana_pllSeqStart */
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+ /* PLL frequency monitor enable */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58069000, ccb->mii + 0x004);
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+
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+ /* RXPMD block */
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+ /* PIPE Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8020, ccb->mii + 0x004);
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+ iowrite32(0x587e8060, ccb->mii + 0x004);
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+
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+ /* CDR int loop locking BW to 1 */
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+ /* CMPMAX & CMPMINTH setting */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58120049, ccb->mii + 0x004);
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+ iowrite32(0x580af30d, ccb->mii + 0x004);
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+
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+ /* CDR int loop acquisition BW to 1 */
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+ /* DEGLITCH MIN & MAX setting */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580e0049, ccb->mii + 0x004);
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+ iowrite32(0x580e6302, ccb->mii + 0x004);
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+
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+ /* TXPMD block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8040, ccb->mii + 0x004);
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+
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+ /* CDR prop loop BW to 1 */
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+ /* Enabling SSC */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580a005c, ccb->mii + 0x004);
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+ iowrite32(0x58061003, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ } else {
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+ } else if (chipinfo->id == BCMA_CHIP_ID_BCM4707) {
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+ /* PLL30 block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8000, ccb->mii + 0x004);
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@ -175,63 +181,6 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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+
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+ /* Deasserting USB3 system reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+ }
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+ break;
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+ case BCMA_CHIP_ID_BCM53018:
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+ /* USB3 PLL Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8000, ccb->mii + 0x004);
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+
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+ /* Assert Ana_Pllseq start */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58061000, ccb->mii + 0x004);
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+
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+ /* Assert CML Divider ratio to 26 */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582a6400, ccb->mii + 0x004);
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+
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+ /* Asserting PLL Reset */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582ec000, ccb->mii + 0x004);
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+
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+ /* Deaaserting PLL Reset */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582e8000, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+
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+ /* Deasserting USB3 system reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+
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+ /* PLL frequency monitor enable */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58069000, ccb->mii + 0x004);
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+
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+ /* PIPE Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8060, ccb->mii + 0x004);
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+
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+ /* CMPMAX & CMPMINTH setting */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580af30d, ccb->mii + 0x004);
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+
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+ /* DEGLITCH MIN & MAX setting */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580e6302, ccb->mii + 0x004);
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+
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+ /* TXPMD block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8040, ccb->mii + 0x004);
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+
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+ /* Enabling SSC */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58061003, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+
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+ break;
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+ }
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+out:
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+ if (dmu)
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@ -258,7 +207,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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static int bcma_hcd_probe(struct bcma_device *core)
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{
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int err;
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@@ -364,6 +580,11 @@ static int bcma_hcd_probe(struct bcma_de
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@@ -364,6 +529,11 @@ static int bcma_hcd_probe(struct bcma_de
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if (err)
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return err;
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break;
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@ -270,7 +219,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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default:
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return -ENODEV;
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}
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@@ -377,11 +598,14 @@ static void bcma_hcd_remove(struct bcma_
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@@ -377,11 +547,14 @@ static void bcma_hcd_remove(struct bcma_
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struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
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struct platform_device *ohci_dev = usb_dev->ohci_dev;
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struct platform_device *ehci_dev = usb_dev->ehci_dev;
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@ -285,7 +234,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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bcma_core_disable(dev, 0);
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}
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@@ -418,6 +642,7 @@ static int bcma_hcd_resume(struct bcma_d
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@@ -418,6 +591,7 @@ static int bcma_hcd_resume(struct bcma_d
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static const struct bcma_device_id bcma_hcd_table[] = {
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BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
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BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
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