parent
0799de6d9e
commit
73ea3c3f9c
@ -1,59 +1,150 @@ |
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1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
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since the CNS3xxx SOCs have ARM11 MPcore CPU.
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2. Enable mpcore_watchdog option as module to default configuration at
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arch/arm/configs/cns3420vb_defconfig.
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Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
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Add a watchdog driver for ARM MPcore processors.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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arch/arm/Kconfig | 1 +
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arch/arm/configs/cns3420vb_defconfig | 2 ++
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arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++
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3 files changed, 25 insertions(+), 0 deletions(-)
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--- a/arch/arm/configs/cns3420vb_defconfig
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+++ b/arch/arm/configs/cns3420vb_defconfig
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@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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+CONFIG_WATCHDOG=y
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+CONFIG_MPCORE_WATCHDOG=m
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_MMC=y
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us
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},
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};
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--- a/drivers/watchdog/Kconfig
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+++ b/drivers/watchdog/Kconfig
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@@ -324,6 +324,13 @@ config KS8695_WATCHDOG
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Watchdog timer embedded into KS8695 processor. This will reboot your
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system when the timeout is reached.
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+/* Watchdog */
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+static struct resource cns3xxx_watchdog_resources[] = {
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+ [0] = {
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+ .start = CNS3XXX_TC11MP_TWD_BASE,
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+ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = IRQ_LOCALWDOG,
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+ .end = IRQ_LOCALWDOG,
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+ .flags = IORESOURCE_IRQ,
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+ }
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+config MPCORE_WATCHDOG
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+ tristate "MPcore watchdog"
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+ depends on HAVE_ARM_TWD
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+ select WATCHDOG_CORE
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+ help
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+ Watchdog timer embedded into the MPcore system
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+
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config HAVE_S3C2410_WATCHDOG
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bool
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help
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--- a/drivers/watchdog/Makefile
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+++ b/drivers/watchdog/Makefile
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@@ -47,6 +47,7 @@ obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
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obj-$(CONFIG_977_WATCHDOG) += wdt977.o
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obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
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obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
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+obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
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obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
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obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
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obj-$(CONFIG_SAMA5D4_WATCHDOG) += sama5d4_wdt.o
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--- /dev/null
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+++ b/drivers/watchdog/mpcore_wdt.c
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@@ -0,0 +1,117 @@
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+/*
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+ * Watchdog driver for ARM MPcore
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+ *
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+ * Copyright (C) 2017 Felix Fietkau <nbd@nbd.name>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/watchdog.h>
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+#include <linux/platform_device.h>
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+#include <linux/io.h>
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+#include <asm/smp_twd.h>
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+
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+static void __iomem *wdt_base;
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+static int wdt_timeout = 60;
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+
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+static int mpcore_wdt_keepalive(struct watchdog_device *wdd)
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+{
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+ static int perturb;
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+ u32 count;
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+
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+ count = ioread32(wdt_base + TWD_WDOG_COUNTER);
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+ count = (~0U - count) * HZ / 5;
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+ count /= 256; /* prescale */
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+ count *= wdt_timeout;
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+
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+ /* Reload register needs a different value on each refresh */
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+ count += perturb;
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+ perturb = !perturb;
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+
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+ iowrite32(count, wdt_base + TWD_WDOG_LOAD);
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+
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+ return 0;
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+}
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+
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+static int mpcore_wdt_start(struct watchdog_device *wdd)
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+{
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+ mpcore_wdt_keepalive(wdd);
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+
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+ /* prescale = 256, mode = 1, enable = 1 */
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+ iowrite32(0x0000FF09, wdt_base + TWD_WDOG_CONTROL);
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+
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+ return 0;
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+}
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+
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+static int mpcore_wdt_stop(struct watchdog_device *wdd)
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+{
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+ iowrite32(0x12345678, wdt_base + TWD_WDOG_DISABLE);
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+ iowrite32(0x87654321, wdt_base + TWD_WDOG_DISABLE);
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+ iowrite32(0x0, wdt_base + TWD_WDOG_CONTROL);
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+
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+ return 0;
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+}
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+
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+static int mpcore_wdt_set_timeout(struct watchdog_device *wdd,
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+ unsigned int timeout)
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+{
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+ mpcore_wdt_stop(wdd);
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+ wdt_timeout = timeout;
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+ mpcore_wdt_start(wdd);
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+
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+ return 0;
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+}
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+
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+static const struct watchdog_info mpcore_wdt_info = {
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+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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+ .identity = "MPcore Watchdog",
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+};
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+
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+static const struct watchdog_ops mpcore_wdt_ops = {
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+ .owner = THIS_MODULE,
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+ .start = mpcore_wdt_start,
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+ .stop = mpcore_wdt_stop,
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+ .ping = mpcore_wdt_keepalive,
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+ .set_timeout = mpcore_wdt_set_timeout,
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+};
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+
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+static struct watchdog_device mpcore_wdt = {
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+ .info = &mpcore_wdt_info,
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+ .ops = &mpcore_wdt_ops,
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+ .min_timeout = 1,
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+ .max_timeout = 65535,
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+};
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+
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+static struct platform_device cns3xxx_watchdog_device = {
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+ .name = "mpcore_wdt",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
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+ .resource = cns3xxx_watchdog_resources,
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+static int mpcore_wdt_probe(struct platform_device *pdev)
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+{
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+ struct resource *res;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!res)
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+ return -ENODEV;
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+
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+ wdt_base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(wdt_base))
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+ return PTR_ERR(wdt_base);
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+
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+ watchdog_register_device(&mpcore_wdt);
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+ return 0;
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+}
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+
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+static int mpcore_wdt_remove(struct platform_device *dev)
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+{
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+ watchdog_unregister_device(&mpcore_wdt);
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+ return 0;
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+}
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+
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+static struct platform_driver mpcore_wdt_driver = {
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+ .probe = mpcore_wdt_probe,
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+ .remove = mpcore_wdt_remove,
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+ .driver = {
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+ .name = "mpcore_wdt",
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+ },
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+};
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+
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/*
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* Initialization
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*/
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static struct platform_device *cns3420_pdevs[] __initdata = {
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+ &cns3xxx_watchdog_device,
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&cns3420_nor_pdev,
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&cns3xxx_usb_ehci_device,
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&cns3xxx_usb_ohci_device,
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+module_platform_driver(mpcore_wdt_driver);
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+MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
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+MODULE_LICENSE("GPL");
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