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@ -396,7 +396,7 @@ |
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -955,6 +967,8 @@ static void local_r4k_flush_cache_sigtra
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@@ -957,6 +969,8 @@ static void local_r4k_flush_cache_sigtra
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}
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R4600_HIT_CACHEOP_WAR_IMPL;
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@ -405,7 +405,7 @@ |
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if (!cpu_has_ic_fills_f_dc) {
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if (dc_lsize)
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vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
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@@ -1843,6 +1857,17 @@ static void coherency_setup(void)
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@@ -1845,6 +1859,17 @@ static void coherency_setup(void)
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_type()) {
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@ -423,7 +423,7 @@ |
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case CPU_R4000PC:
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -1889,6 +1914,15 @@ void r4k_cache_init(void)
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@@ -1891,6 +1916,15 @@ void r4k_cache_init(void)
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extern void build_copy_page(void);
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struct cpuinfo_mips *c = ¤t_cpu_data;
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@ -439,7 +439,7 @@ |
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probe_pcache();
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probe_vcache();
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setup_scache();
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@@ -1966,7 +2000,15 @@ void r4k_cache_init(void)
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@@ -1968,7 +2002,15 @@ void r4k_cache_init(void)
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*/
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local_r4k___flush_cache_all(NULL);
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