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@ -203,6 +203,23 @@ |
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#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR) |
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/* EIU - external interrupt controller */ |
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/** EIU - base address */ |
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#define IFXMIPS_EIU_BASE_ADDR 0xBF101000 |
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/** EIU - control register */ |
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#define IFXMIPS_EIU_EXIN_C ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x0000)) |
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/** EIU - interrupt node interrupt capture */ |
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#define IFXMIPS_EIU_INIC ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x0004)) |
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/** EIU - interrupt node control */ |
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#define IFXMIPS_EIU_INC ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x0008)) |
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/** EIU - interrupt node enable */ |
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#define IFXMIPS_EIU_INEN ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x000C)) |
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/** NMI - control */ |
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#define IFXMIPS_NMI_CR ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x00F0)) |
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/** NMI - status */ |
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#define IFXMIPS_NMI_SR (( u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x00F4)) |
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/*------------ ETOP */ |
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